include/configs/phycore_imx8mm.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later
   2  *
   3  * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
   4  * Author: Teresa Remmet <t.remmet@phytec.de>
   5  */
   6
   7 #ifndef __PHYCORE_IMX8MM_H
   8 #define __PHYCORE_IMX8MM_H
   9
  10 #include <linux/sizes.h>
  11 #include <linux/stringify.h>
  12 #include <asm/arch/imx-regs.h>
  13
  14 #define CONFIG_SYS_BOOTM_LEN            SZ_64M
  15 #define CONFIG_SPL_MAX_SIZE             (148 * SZ_1K)
  16 #define CONFIG_SYS_MONITOR_LEN          SZ_512K
  17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  18 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
  19 #define CONFIG_SYS_UBOOT_BASE \
  20                 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  21
  22 #ifdef CONFIG_SPL_BUILD
  23 #define CONFIG_SPL_STACK                0x920000
  24 #define CONFIG_SPL_BSS_START_ADDR       0x910000
  25 #define CONFIG_SPL_BSS_MAX_SIZE         SZ_8K
  26 #define CONFIG_SYS_SPL_MALLOC_START     0x42200000
  27 #define CONFIG_SYS_SPL_MALLOC_SIZE      SZ_512K
  28
  29 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  30 #define CONFIG_MALLOC_F_ADDR            0x930000
  31 /* For RAW image gives a error info not panic */
  32 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  33 #endif
  34
  35 #define CONFIG_EXTRA_ENV_SETTINGS \
  36         "image=Image\0" \
  37         "console=ttymxc2,115200\0" \
  38         "fdt_addr=0x48000000\0" \
  39         "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
  40         "ip_dyn=yes\0" \
  41         "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
  42         "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  43         "mmcroot=2\0" \
  44         "mmcautodetect=yes\0" \
  45         "mmcargs=setenv bootargs console=${console} " \
  46                 "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
  47         "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  48         "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  49         "mmcboot=echo Booting from mmc ...; " \
  50                 "run mmcargs; " \
  51                 "if run loadfdt; then " \
  52                         "booti ${loadaddr} - ${fdt_addr}; " \
  53                 "else " \
  54                         "echo WARN: Cannot load the DT; " \
  55                 "fi;\0 " \
  56         "nfsroot=/nfs\0" \
  57         "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
  58                 "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
  59         "netboot=echo Booting from net ...; " \
  60                 "run netargs; " \
  61                 "if test ${ip_dyn} = yes; then " \
  62                         "setenv get_cmd dhcp; " \
  63                 "else " \
  64                         "setenv get_cmd tftp; " \
  65                 "fi; " \
  66                 "${get_cmd} ${loadaddr} ${image}; " \
  67                 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  68                         "booti ${loadaddr} - ${fdt_addr}; " \
  69                 "else " \
  70                         "echo WARN: Cannot load the DT; " \
  71                 "fi;\0" \
  72
  73 #define CONFIG_BOOTCOMMAND \
  74         "mmc dev ${mmcdev}; if mmc rescan; then " \
  75                 "if run loadimage; then " \
  76                         "run mmcboot; " \
  77                 "else run netboot; " \
  78                 "fi; " \
  79         "fi;"
  80
  81 /* Link Definitions */
  82
  83 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
  84 #define CONFIG_SYS_INIT_RAM_SIZE        SZ_512K
  85 #define CONFIG_SYS_INIT_SP_OFFSET \
  86         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  87 #define CONFIG_SYS_INIT_SP_ADDR \
  88         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  89
  90 #define CONFIG_MMCROOT                  "/dev/mmcblk2p2"  /* USDHC3 */
  91
  92 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  93
  94 #define PHYS_SDRAM                      0x40000000
  95 #define PHYS_SDRAM_SIZE                 SZ_2G /* 2GB DDR */
  96
  97 /* UART */
  98 #define CONFIG_MXC_UART_BASE            UART3_BASE_ADDR
  99
 100 /* Monitor Command Prompt */
 101 #define CONFIG_SYS_CBSIZE               SZ_2K
 102 #define CONFIG_SYS_MAXARGS              64
 103 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 104
 105 /* USDHC */
 106 #define CONFIG_SYS_FSL_USDHC_NUM        2
 107 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
 108 #define CONFIG_SYS_MMC_IMG_LOAD_PART    1
 109
 110 #endif /* __PHYCORE_IMX8MM_H */