global: Move remaining CONFIG_SYS_* to CFG_SYS_*
[platform/kernel/u-boot.git] / include / configs / pg-wcom-expu1.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2020 Hitachi ABB Power Grids
4  */
5
6 #ifndef __CONFIG_PG_WCOM_EXPU1_H
7 #define __CONFIG_PG_WCOM_EXPU1_H
8
9 #define WCOM_EXPU1
10 #define CONFIG_HOSTNAME                         "EXPU1"
11
12 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT       "ubi0"
13 #define CONFIG_KM_UBI_PARTITION_NAME_APP        "ubi1"
14
15 /* CLIPS FPGA Definitions */
16 #define CFG_SYS_CSPR3_EXT       (0x00)
17 #define CFG_SYS_CSPR3   (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \
18                                 CSPR_PORT_SIZE_8 | \
19                                 CSPR_MSEL_GPCM | \
20                                 CSPR_V)
21 #define CFG_SYS_AMASK3  IFC_AMASK(64 * 1024)
22 #define CFG_SYS_CSOR3   (CSOR_GPCM_ADM_SHIFT(0x4) | \
23                                 CSOR_GPCM_TRHZ_40)
24 #define CFG_SYS_CS3_FTIM0       (FTIM0_GPCM_TACSE(0x6) | \
25                                 FTIM0_GPCM_TEADC(0x7) | \
26                                 FTIM0_GPCM_TEAHC(0x2))
27 #define CFG_SYS_CS3_FTIM1       (FTIM1_GPCM_TACO(0x2) | \
28                                 FTIM1_GPCM_TRAD(0x12))
29 #define CFG_SYS_CS3_FTIM2       (FTIM2_GPCM_TCS(0x3) | \
30                                 FTIM2_GPCM_TCH(0x1) | \
31                                 FTIM2_GPCM_TWP(0x12))
32 #define CFG_SYS_CS3_FTIM3       0x04000000
33
34 /* PRST */
35 #define WCOM_CLIPS_RST          0
36 #define WCOM_QSFP_RST           1
37 #define WCOM_PHY_RST            2
38 #define WCOM_TMG_RST            3
39 #define KM_DBG_ETH_RST          15
40
41 /* QRIO GPIOs used for deblocking */
42 #define KM_I2C_DEBLOCK_PORT     QRIO_GPIO_A
43 #define KM_I2C_DEBLOCK_SCL      20
44 #define KM_I2C_DEBLOCK_SDA      21
45
46 /* ZL30343 on SPI */
47 #define WCOM_ZL30343_CFG_ADDR   0xe8070000
48 #define WCOM_ZL30343_SPI_BUS    0
49 #define WCOM_ZL30343_CS 0
50
51 #include "km/pg-wcom-ls102xa.h"
52
53 #endif /* __CONFIG_PG_WCOM_EXPU1_H */