include/configs/pdm360ng.h

   1 /*
   2  * (C) Copyright 2009-2010
   3  * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * pdm360ng board configuration file
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 #define CONFIG_PDM360NG 1
  16
  17 /*
  18  * Memory map for the PDM360NG board:
  19  *
  20  * 0x0000_0000 - 0x1FFF_FFFF    DDR RAM (512 MB)
  21  * 0x2000_0000 - 0x3FFF_FFFF    reserved (DDR RAM (512 MB)
  22  * 0x5000_0000 - 0x5001_FFFF    SRAM (128 KB)
  23  * 0x5004_0000 - 0x5005_FFFF    MRAM (CS2) (128 KB)
  24  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
  25  * 0xF000_0000 - 0xF7FF_FFFF    NOR FLASH (CS0) (128 MB)
  26  * 0xF800_0000 - 0xFFFF_FFFF    NOR FLASH (CS1) (128 MB) optional
  27  */
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_E300             1       /* E300 Family */
  33 #define CONFIG_FSL_DIU_FB       1       /* FSL DIU */
  34
  35 #define CONFIG_SYS_TEXT_BASE    0xF0000000
  36
  37 /* Used for silent command in environment */
  38 #define CONFIG_SYS_DEVICE_NULLDEV
  39
  40 /* Video */
  41 #define CONFIG_VIDEO
  42
  43 #if defined(CONFIG_VIDEO)
  44 #define CONFIG_CFB_CONSOLE
  45 #define CONFIG_VGA_AS_SINGLE_DEVICE
  46 #define CONFIG_SPLASH_SCREEN
  47 #define CONFIG_VIDEO_LOGO
  48 #define CONFIG_VIDEO_BMP_RLE8
  49 #endif
  50
  51 #define CONFIG_SYS_MPC512X_CLKIN        33333333        /* in Hz */
  52
  53 #define CONFIG_MISC_INIT_R
  54
  55 #define CONFIG_SYS_IMMR                 0x80000000
  56 #define CONFIG_SYS_DIU_ADDR             ((CONFIG_SYS_IMMR) + 0x2100)
  57
  58 /*
  59  * DDR Setup
  60  */
  61
  62 /* DDR is system memory */
  63 #define CONFIG_SYS_DDR_BASE             0x00000000
  64 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  65 #define CONFIG_SYS_MAX_RAM_SIZE         0x40000000
  66
  67 /* DDR pin mux and slew rate */
  68 #define CONFIG_SYS_IOCTRL_MUX_DDR       0x00000012
  69
  70 /* Manually set all parameters as there's no SPD etc. */
  71 /*
  72  * DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3
  73  *
  74  * SYS_CFG:
  75  *      [31:31] MDDRC Soft Reset:       Diabled
  76  *      [30:30] DRAM CKE pin:           Enabled
  77  *      [29:29] DRAM CLK:               Enabled
  78  *      [28:28] Command Mode:           Enabled (For initialization only)
  79  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
  80  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
  81  *      [20:19] Read Test:              DON'T USE
  82  *      [18:18] Self Refresh:           Enabled
  83  *      [17:17] 16bit Mode:             Disabled
  84  *      [16:13] Read Delay:             3
  85  *      [12:12] Half DQS Delay:         Disabled
  86  *      [11:11] Quarter DQS Delay:      Disabled
  87  *      [10:08] Write Delay:            2
  88  *      [07:07] Early ODT:              Disabled
  89  *      [06:06] On DIE Termination:     Enabled
  90  *      [05:05] FIFO Overflow Clear:    DON'T USE here
  91  *      [04:04] FIFO Underflow Clear:   DON'T USE here
  92  *      [03:03] FIFO Overflow Pending:  DON'T USE here
  93  *      [02:02] FIFO Underlfow Pending: DON'T USE here
  94  *      [01:01] FIFO Overlfow Enabled:  Enabled
  95  *      [00:00] FIFO Underflow Enabled: Enabled
  96  * TIME_CFG0
  97  *      [31:16] DRAM Refresh Time:      0 CSB clocks
  98  *      [15:8]  DRAM Command Time:      0 CSB clocks
  99  *      [07:00] DRAM Precharge Time:    0 CSB clocks
 100  * TIME_CFG1
 101  *      [31:26] DRAM tRFC:
 102  *      [25:21] DRAM tWR1:
 103  *      [20:17] DRAM tWRT1:
 104  *      [16:11] DRAM tDRR:
 105  *      [10:05] DRAM tRC:
 106  *      [04:00] DRAM tRAS:
 107  * TIME_CFG2
 108  *      [31:28] DRAM tRCD:
 109  *      [27:23] DRAM tFAW:
 110  *      [22:19] DRAM tRTW1:
 111  *      [18:15] DRAM tCCD:
 112  *      [14:10] DRAM tRTP:
 113  *      [09:05] DRAM tRP:
 114  *      [04:00] DRAM tRPA
 115  */
 116 #define CONFIG_SYS_MDDRC_SYS_CFG        0xEA804A40
 117 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x030C3D2E
 118 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x68EC1168
 119 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x34310864
 120
 121 /*
 122  * Alternative 1: small RAM (128 MB) configuration
 123  */
 124 #define CONFIG_SYS_MDDRC_SYS_CFG_ALT1   0xE8604A40
 125 #define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1 0x030C3D2E
 126 #define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1 0x3CEC1168
 127 #define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 0x33310863
 128
 129 #define CONFIG_SYS_MDDRC_SYS_CFG_EN     0xF0000000
 130
 131 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
 132 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
 133 #define CONFIG_SYS_DDRCMD_EM2           0x01020000  /* EMR2 */
 134 #define CONFIG_SYS_DDRCMD_EM3           0x01030000  /* EMR3 */
 135 /* EMR with 150 ohm ODT todo: verify */
 136 #define CONFIG_SYS_DDRCMD_EN_DLL        0x01010040
 137 #define CONFIG_SYS_DDRCMD_RES_DLL       0x01000100
 138 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
 139 #define CONFIG_SYS_MICRON_INIT_DEV_OP   0x01000432
 140 /* EMR with 150 ohm ODT todo: verify */
 141 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   0x010107C0
 142 /* EMR new command with 150 ohm ODT todo: verify */
 143 #define CONFIG_SYS_DDRCMD_OCD_EXIT      0x01010440
 144
 145 /* DDR Priority Manager Configuration */
 146 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
 147 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
 148 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
 149 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
 150 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
 151 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
 152 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
 153 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
 154 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
 155 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
 156 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
 157 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
 158 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
 159 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
 160 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
 161 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
 162 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
 163 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
 164 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
 165 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
 166 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
 167 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
 168 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
 169
 170 /*
 171  * NOR FLASH on the Local Bus
 172  */
 173 #define CONFIG_SYS_FLASH_CFI            /* use Common Flash Interface */
 174 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 175 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 176
 177 #define CONFIG_SYS_FLASH_BASE           0xF0000000 /* start of FLASH-Bank0 */
 178 #define CONFIG_SYS_FLASH_SIZE           0x08000000 /* max size of a Bank */
 179 /* start of FLASH-Bank1 */
 180 #define CONFIG_SYS_FLASH1_BASE          (CONFIG_SYS_FLASH_BASE + \
 181                                          CONFIG_SYS_FLASH_SIZE)
 182 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per device */
 183 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 184 #define CONFIG_SYS_FLASH_BANKS_LIST \
 185         {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE}
 186
 187 #define CONFIG_SYS_SRAM_BASE            0x50000000
 188 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
 189
 190 #define CONFIG_SYS_CS1_START            CONFIG_SYS_FLASH1_BASE
 191 #define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_FLASH_SIZE
 192
 193 /* ALE active low, data size 4 bytes */
 194 #define CONFIG_SYS_CS0_CFG              0x05059350
 195 /* ALE active low, data size 4 bytes */
 196 #define CONFIG_SYS_CS1_CFG              0x05059350
 197
 198 #define CONFIG_SYS_MRAM_BASE            0x50040000
 199 #define CONFIG_SYS_MRAM_SIZE            0x00020000
 200 #define CONFIG_SYS_CS2_START            CONFIG_SYS_MRAM_BASE
 201 #define CONFIG_SYS_CS2_SIZE             CONFIG_SYS_MRAM_SIZE
 202
 203 /* ALE active low, data size 4 bytes */
 204 #define CONFIG_SYS_CS2_CFG              0x05059110
 205
 206 /* alt. CS timing for CS0, CS1, CS2 */
 207 #define CONFIG_SYS_CS_ALETIMING         0x00000007
 208
 209 /*
 210  * NAND FLASH
 211  */
 212 #define CONFIG_CMD_NAND                 /* enable NAND support */
 213 #define CONFIG_NAND_MPC5121_NFC
 214 #define CONFIG_SYS_NAND_BASE            0x40000000
 215 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 216 #define CONFIG_SYS_NAND_SELECT_DEVICE   /* driver supports mutipl. chips */
 217
 218 /*
 219  * Configuration parameters for MPC5121 NAND driver
 220  */
 221 #define CONFIG_FSL_NFC_WIDTH 1
 222 #define CONFIG_FSL_NFC_WRITE_SIZE 2048
 223 #define CONFIG_FSL_NFC_SPARE_SIZE 64
 224 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
 225
 226 /*
 227  * Dynamic MTD partition support
 228  */
 229 #define CONFIG_CMD_MTDPARTS
 230 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 231 #define CONFIG_FLASH_CFI_MTD
 232 #define MTDIDS_DEFAULT          "nor0=f0000000.flash,nor1=f8000000.flash," \
 233                                                 "nand0=MPC5121 NAND"
 234
 235 /*
 236  * Flash layout
 237  */
 238 #define MTDPARTS_DEFAULT        "mtdparts=f0000000.flash:512k(u-boot)," \
 239                                                 "256k(environment1),"   \
 240                                                 "256k(environment2),"   \
 241                                                 "256k(splash-factory)," \
 242                                                 "2m(FIT: recovery),"    \
 243                                                 "4608k(fs-recovery),"   \
 244                                                 "256k(splash-customer),"\
 245                                                 "5m(FIT: kernel+dtb),"  \
 246                                                 "64m(rootfs squash)ro," \
 247                                                 "51m(userfs ubi);"      \
 248                                         "f8000000.flash:-(unused);"     \
 249                                         "MPC5121 NAND:1024m(extended-userfs)"
 250
 251 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* Start of monitor */
 252 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* 512 kB for monitor */
 253 #ifdef  CONFIG_FSL_DIU_FB
 254 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024) /* for malloc */
 255 #else
 256 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 257 #endif
 258
 259 /*
 260  * Serial Port
 261  */
 262 #define CONFIG_CONS_INDEX     1
 263
 264 /*
 265  * Serial console configuration
 266  */
 267 #define CONFIG_PSC_CONSOLE      6       /* console is on PSC6 */
 268 #if CONFIG_PSC_CONSOLE != 6
 269 #error CONFIG_PSC_CONSOLE must be 6
 270 #endif
 271
 272 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC6_TX_SIZE
 273 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC6_TX_ADDR
 274 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC6_RX_SIZE
 275 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC6_RX_ADDR
 276
 277 /*
 278  * Clocks in use
 279  */
 280 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
 281                          CLOCK_SCCR1_LPC_EN |                           \
 282                          CLOCK_SCCR1_NFC_EN |                           \
 283                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
 284                          CLOCK_SCCR1_PSCFIFO_EN |                       \
 285                          CLOCK_SCCR1_DDR_EN |                           \
 286                          CLOCK_SCCR1_FEC_EN |                           \
 287                          CLOCK_SCCR1_TPR_EN)
 288
 289 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN |           \
 290                          CLOCK_SCCR2_SPDIF_EN |         \
 291                          CLOCK_SCCR2_DIU_EN |           \
 292                          CLOCK_SCCR2_I2C_EN)
 293
 294 /*
 295  * Used PSC UART devices
 296  */
 297 #define CONFIG_SYS_PSC1
 298 #define CONFIG_SYS_PSC4
 299 #define CONFIG_SYS_PSC6
 300
 301 /*
 302  * Co-processor communication parameters
 303  */
 304 #define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY   5000
 305 #define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE     38400
 306
 307 /*
 308  * I2C
 309  */
 310 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 311 #define CONFIG_I2C_MULTI_BUS
 312 #define CONFIG_I2C_CMD_TREE
 313 /* I2C speed and slave address */
 314 #define CONFIG_SYS_I2C_SPEED            100000
 315 #define CONFIG_SYS_I2C_SLAVE            0x7F
 316
 317 /*
 318  * IIM - IC Identification Module
 319  */
 320 #undef CONFIG_FSL_IIM
 321
 322 /*
 323  * EEPROM configuration
 324  */
 325 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16-bit EEPROM addr */
 326 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* ST AT24C01 */
 327 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* 10ms of delay */
 328 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4       /* 16-Byte Write Mode */
 329
 330 /*
 331  * MAC addr in EEPROM
 332  */
 333 #define CONFIG_SYS_I2C_EEPROM_BUS_NUM           0
 334 #define CONFIG_SYS_I2C_EEPROM_MAC_OFFSET        0x10
 335 /*
 336  * Enabled only to delete "ethaddr" before testing
 337  * "ethaddr" setting from EEPROM
 338  */
 339 #define CONFIG_ENV_OVERWRITE
 340
 341 /*
 342  * Ethernet configuration
 343  */
 344 #define CONFIG_MPC512x_FEC      1
 345 #define CONFIG_PHY_ADDR         0x1F
 346 #define CONFIG_MII              1       /* MII PHY management   */
 347 #define CONFIG_FEC_AN_TIMEOUT   1
 348 #define CONFIG_HAS_ETH0
 349
 350 /*
 351  * Configure on-board RTC
 352  */
 353 #define CONFIG_RTC_M41T62                       /* use M41T00 rtc via i2c */
 354 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68      */
 355
 356 /*
 357  * Environment
 358  */
 359 #define CONFIG_ENV_IS_IN_FLASH  1
 360 /* This has to be a multiple of the Flash sector size */
 361 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 362                                  CONFIG_SYS_MONITOR_LEN)
 363 #define CONFIG_ENV_SIZE         0x2000
 364 #define CONFIG_ENV_SECT_SIZE    0x40000         /* one sector (256K) for env */
 365
 366 /* Address and size of Redundant Environment Sector     */
 367 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 368 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 369
 370 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 371 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 372
 373 #define CONFIG_CMD_DATE
 374 #define CONFIG_CMD_EEPROM
 375 #define CONFIG_CMD_REGINFO
 376
 377 #undef CONFIG_CMD_FUSE
 378
 379 #ifdef CONFIG_VIDEO
 380 #define CONFIG_CMD_BMP
 381 #endif
 382
 383 /*
 384  * Miscellaneous configurable options
 385  */
 386 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 387 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 388
 389 #ifdef CONFIG_CMD_KGDB
 390         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 391 #else
 392         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 393 #endif
 394
 395 /* Print Buffer Size */
 396 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 397 /* Max number of command args */
 398 #define CONFIG_SYS_MAXARGS      16
 399 /* Boot Argument Buffer Size */
 400 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 401 /* Decrementer freq: 1ms ticks */
 402
 403 /*
 404  * For booting Linux, the board info and command line data
 405  * have to be in the first 256 MB of memory, since this is
 406  * the maximum mapped by the Linux kernel during initialization.
 407  */
 408 /* Initial Memory map for Linux */
 409 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 410
 411 /* Cache Configuration */
 412 #define CONFIG_SYS_DCACHE_SIZE          32768
 413 #define CONFIG_SYS_CACHELINE_SIZE       32
 414 #ifdef CONFIG_CMD_KGDB
 415 /* log base 2 of the above value */
 416 #define CONFIG_SYS_CACHELINE_SHIFT      5
 417 #endif
 418
 419 #define CONFIG_SYS_HID0_INIT    0x000000000
 420 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
 421 #define CONFIG_SYS_HID2 HID2_HBE
 422
 423 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 424
 425 #ifdef CONFIG_CMD_KGDB
 426 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 427 #endif
 428
 429 /* POST support */
 430 #define CONFIG_POST             (CONFIG_SYS_POST_COPROC)
 431
 432 /*
 433  * Environment Configuration
 434  */
 435 #define CONFIG_TIMESTAMP
 436
 437 #define CONFIG_HOSTNAME         pdm360ng
 438 /* default location for tftp and bootm */
 439 #define CONFIG_LOADADDR         400000
 440
 441
 442 #define CONFIG_PREBOOT  "echo;" \
 443         "echo PDM360NG SAMPLE;" \
 444         "echo"
 445
 446 #define CONFIG_BOOTCOMMAND      "run env_cont"
 447
 448 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
 449
 450 #define OF_CPU                  "PowerPC,5121@0"
 451 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
 452 #define OF_TBCLK                (bd->bi_busfreq / 4)
 453 #define OF_STDOUT_PATH          "/soc@80000000/serial@11600"
 454
 455 /*
 456  * Include common options for all mpc5121 boards
 457  */
 458 #include "mpc5121-common.h"
 459
 460 #endif  /* __CONFIG_H */