1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
7 * QorIQ RDB boards configuration file
12 #if defined(CONFIG_TARGET_P1020MBG)
13 #define CONFIG_BOARDNAME "P1020MBG-PC"
14 #define CONFIG_VSC7385_ENET
16 #define __SW_BOOT_MASK 0x03
17 #define __SW_BOOT_NOR 0xe4
18 #define __SW_BOOT_SD 0x54
19 #define CONFIG_SYS_L2_SIZE (256 << 10)
22 #if defined(CONFIG_TARGET_P1020UTM)
23 #define CONFIG_BOARDNAME "P1020UTM-PC"
24 #define __SW_BOOT_MASK 0x03
25 #define __SW_BOOT_NOR 0xe0
26 #define __SW_BOOT_SD 0x50
27 #define CONFIG_SYS_L2_SIZE (256 << 10)
30 #if defined(CONFIG_TARGET_P1020RDB_PC)
31 #define CONFIG_BOARDNAME "P1020RDB-PC"
32 #define CONFIG_NAND_FSL_ELBC
33 #define CONFIG_VSC7385_ENET
35 #define __SW_BOOT_MASK 0x03
36 #define __SW_BOOT_NOR 0x5c
37 #define __SW_BOOT_SPI 0x1c
38 #define __SW_BOOT_SD 0x9c
39 #define __SW_BOOT_NAND 0xec
40 #define __SW_BOOT_PCIE 0x6c
41 #define CONFIG_SYS_L2_SIZE (256 << 10)
45 * P1020RDB-PD board has user selectable switches for evaluating different
46 * frequency and boot options for the P1020 device. The table that
47 * follow describe the available options. The front six binary number was in
48 * accordance with SW3[1:6].
49 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
50 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
51 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
52 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
53 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
54 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
55 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
57 #if defined(CONFIG_TARGET_P1020RDB_PD)
58 #define CONFIG_BOARDNAME "P1020RDB-PD"
59 #define CONFIG_NAND_FSL_ELBC
60 #define CONFIG_VSC7385_ENET
62 #define __SW_BOOT_MASK 0x03
63 #define __SW_BOOT_NOR 0x64
64 #define __SW_BOOT_SPI 0x34
65 #define __SW_BOOT_SD 0x24
66 #define __SW_BOOT_NAND 0x44
67 #define __SW_BOOT_PCIE 0x74
68 #define CONFIG_SYS_L2_SIZE (256 << 10)
70 * Dynamic MTD Partition support with mtdparts
74 #if defined(CONFIG_TARGET_P1021RDB)
75 #define CONFIG_BOARDNAME "P1021RDB-PC"
76 #define CONFIG_NAND_FSL_ELBC
77 #define CONFIG_VSC7385_ENET
78 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
79 addresses in the LBC */
80 #define __SW_BOOT_MASK 0x03
81 #define __SW_BOOT_NOR 0x5c
82 #define __SW_BOOT_SPI 0x1c
83 #define __SW_BOOT_SD 0x9c
84 #define __SW_BOOT_NAND 0xec
85 #define __SW_BOOT_PCIE 0x6c
86 #define CONFIG_SYS_L2_SIZE (256 << 10)
88 * Dynamic MTD Partition support with mtdparts
92 #if defined(CONFIG_TARGET_P1024RDB)
93 #define CONFIG_BOARDNAME "P1024RDB"
94 #define CONFIG_NAND_FSL_ELBC
96 #define __SW_BOOT_MASK 0xf3
97 #define __SW_BOOT_NOR 0x00
98 #define __SW_BOOT_SPI 0x08
99 #define __SW_BOOT_SD 0x04
100 #define __SW_BOOT_NAND 0x0c
101 #define CONFIG_SYS_L2_SIZE (256 << 10)
104 #if defined(CONFIG_TARGET_P1025RDB)
105 #define CONFIG_BOARDNAME "P1025RDB"
106 #define CONFIG_NAND_FSL_ELBC
109 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
110 addresses in the LBC */
111 #define __SW_BOOT_MASK 0xf3
112 #define __SW_BOOT_NOR 0x00
113 #define __SW_BOOT_SPI 0x08
114 #define __SW_BOOT_SD 0x04
115 #define __SW_BOOT_NAND 0x0c
116 #define CONFIG_SYS_L2_SIZE (256 << 10)
119 #if defined(CONFIG_TARGET_P2020RDB)
120 #define CONFIG_BOARDNAME "P2020RDB-PC"
121 #define CONFIG_NAND_FSL_ELBC
122 #define CONFIG_VSC7385_ENET
123 #define __SW_BOOT_MASK 0x03
124 #define __SW_BOOT_NOR 0xc8
125 #define __SW_BOOT_SPI 0x28
126 #define __SW_BOOT_SD 0x68 /* or 0x18 */
127 #define __SW_BOOT_NAND 0xe8
128 #define __SW_BOOT_PCIE 0xa8
129 #define CONFIG_SYS_L2_SIZE (512 << 10)
131 * Dynamic MTD Partition support with mtdparts
136 #define CONFIG_SPL_FLUSH_IMAGE
137 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
138 #define CONFIG_SPL_PAD_TO 0x20000
139 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
140 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
141 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
142 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
143 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
144 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
145 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
146 #ifdef CONFIG_SPL_BUILD
147 #define CONFIG_SPL_COMMON_INIT_DDR
151 #ifdef CONFIG_SPIFLASH
152 #define CONFIG_SPL_SPI_FLASH_MINIMAL
153 #define CONFIG_SPL_FLUSH_IMAGE
154 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
155 #define CONFIG_SPL_PAD_TO 0x20000
156 #define CONFIG_SPL_MAX_SIZE (128 * 1024)
157 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
158 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
159 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
160 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
161 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
162 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
163 #ifdef CONFIG_SPL_BUILD
164 #define CONFIG_SPL_COMMON_INIT_DDR
169 #ifdef CONFIG_TPL_BUILD
170 #define CONFIG_SPL_FLUSH_IMAGE
171 #define CONFIG_SPL_NAND_INIT
172 #define CONFIG_SPL_COMMON_INIT_DDR
173 #define CONFIG_SPL_MAX_SIZE (128 << 10)
174 #define CONFIG_TPL_TEXT_BASE 0xf8f81000
175 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
176 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
177 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
178 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
179 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
180 #elif defined(CONFIG_SPL_BUILD)
181 #define CONFIG_SPL_INIT_MINIMAL
182 #define CONFIG_SPL_FLUSH_IMAGE
183 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
184 #define CONFIG_SPL_MAX_SIZE 4096
185 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
186 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
187 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
188 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
189 #endif /* not CONFIG_TPL_BUILD */
191 #define CONFIG_SPL_PAD_TO 0x20000
192 #define CONFIG_TPL_PAD_TO 0x20000
193 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
194 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
197 #ifndef CONFIG_RESET_VECTOR_ADDRESS
198 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
201 #ifndef CONFIG_SYS_MONITOR_BASE
202 #ifdef CONFIG_TPL_BUILD
203 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
204 #elif defined(CONFIG_SPL_BUILD)
205 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
207 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
211 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
212 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
213 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
214 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
215 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
216 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
218 #define CONFIG_ENV_OVERWRITE
220 #define CONFIG_SYS_SATA_MAX_DEVICE 2
223 #if defined(CONFIG_TARGET_P2020RDB)
224 #define CONFIG_SYS_CLK_FREQ 100000000
226 #define CONFIG_SYS_CLK_FREQ 66666666
228 #define CONFIG_DDR_CLK_FREQ 66666666
230 #define CONFIG_HWCONFIG
232 * These can be toggled for performance analysis, otherwise use default.
234 #define CONFIG_L2_CACHE
237 #define CONFIG_ENABLE_36BIT_PHYS
239 #ifdef CONFIG_PHYS_64BIT
240 #define CONFIG_ADDR_MAP 1
241 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
244 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
245 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
247 #define CONFIG_SYS_CCSRBAR 0xffe00000
248 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
250 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
252 #ifdef CONFIG_SPL_BUILD
253 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
257 #define CONFIG_SYS_DDR_RAW_TIMING
258 #define CONFIG_DDR_SPD
259 #define CONFIG_SYS_SPD_BUS_NUM 1
260 #define SPD_EEPROM_ADDRESS 0x52
262 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
263 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
264 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
266 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
267 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
269 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
270 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
271 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
273 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
275 /* Default settings for DDR3 */
276 #ifndef CONFIG_TARGET_P2020RDB
277 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
278 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
279 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
280 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
281 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
282 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
284 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
285 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
286 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
287 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
289 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
290 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
291 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
292 #define CONFIG_SYS_DDR_RCW_1 0x00000000
293 #define CONFIG_SYS_DDR_RCW_2 0x00000000
294 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
295 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
296 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
297 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
299 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
300 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
301 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
302 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
303 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
304 #define CONFIG_SYS_DDR_MODE_1 0x40461520
305 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
306 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
309 #undef CONFIG_CLOCKS_IN_MHZ
314 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
315 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
316 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
317 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
319 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
320 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
321 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
322 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
323 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
324 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
325 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
329 * Local Bus Definitions
331 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
332 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
333 #define CONFIG_SYS_FLASH_BASE 0xec000000
334 #elif defined(CONFIG_TARGET_P1020UTM)
335 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
336 #define CONFIG_SYS_FLASH_BASE 0xee000000
338 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
339 #define CONFIG_SYS_FLASH_BASE 0xef000000
342 #ifdef CONFIG_PHYS_64BIT
343 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
345 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
348 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
351 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
353 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
354 #define CONFIG_SYS_FLASH_QUIET_TEST
355 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
357 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
359 #undef CONFIG_SYS_FLASH_CHECKSUM
360 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
361 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
363 #define CONFIG_SYS_FLASH_EMPTY_INFO
366 #ifdef CONFIG_NAND_FSL_ELBC
367 #define CONFIG_SYS_NAND_BASE 0xff800000
368 #ifdef CONFIG_PHYS_64BIT
369 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
371 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
374 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
375 #define CONFIG_SYS_MAX_NAND_DEVICE 1
376 #if defined(CONFIG_TARGET_P1020RDB_PD)
377 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
379 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
382 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
383 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
384 | BR_PS_8 /* Port Size = 8 bit */ \
385 | BR_MS_FCM /* MSEL = FCM */ \
387 #if defined(CONFIG_TARGET_P1020RDB_PD)
388 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
389 | OR_FCM_PGS /* Large Page*/ \
397 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
405 #endif /* CONFIG_NAND_FSL_ELBC */
407 #define CONFIG_SYS_INIT_RAM_LOCK
408 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
409 #ifdef CONFIG_PHYS_64BIT
410 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
411 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
412 /* The assembler doesn't like typecast */
413 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
414 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
415 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
417 /* Initial L1 address */
418 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
419 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
420 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
422 /* Size of used area in RAM */
423 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
425 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
426 GENERATED_GBL_DATA_SIZE)
427 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
429 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
430 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
432 #define CONFIG_SYS_CPLD_BASE 0xffa00000
433 #ifdef CONFIG_PHYS_64BIT
434 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
436 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
438 /* CPLD config size: 1Mb */
439 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
441 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
443 #define CONFIG_SYS_PMC_BASE 0xff980000
444 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
445 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
447 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
448 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
452 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
453 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
454 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
455 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
457 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
458 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
459 #ifdef CONFIG_NAND_FSL_ELBC
460 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
461 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
464 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
465 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
468 #ifdef CONFIG_VSC7385_ENET
469 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
471 #ifdef CONFIG_PHYS_64BIT
472 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
474 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
477 #define CONFIG_SYS_VSC7385_BR_PRELIM \
478 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
479 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
480 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
481 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
483 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
484 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
486 /* The size of the VSC7385 firmware image */
487 #define CONFIG_VSC7385_IMAGE_SIZE 8192
491 * Config the L2 Cache as L2 SRAM
493 #if defined(CONFIG_SPL_BUILD)
494 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
495 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
496 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
497 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
498 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
499 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
500 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
501 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
502 #if defined(CONFIG_TARGET_P2020RDB)
503 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
505 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
507 #elif defined(CONFIG_NAND)
508 #ifdef CONFIG_TPL_BUILD
509 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
510 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
511 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
512 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
513 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
514 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
515 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
516 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
518 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
519 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
520 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
521 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
522 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
523 #endif /* CONFIG_TPL_BUILD */
527 /* Serial Port - controlled on board with jumper J8
531 #undef CONFIG_SERIAL_SOFTWARE_FIFO
532 #define CONFIG_SYS_NS16550_SERIAL
533 #define CONFIG_SYS_NS16550_REG_SIZE 1
534 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
535 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
536 #define CONFIG_NS16550_MIN_FUNCTIONS
539 #define CONFIG_SYS_BAUDRATE_TABLE \
540 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
542 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
543 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
546 #define CONFIG_SYS_I2C
547 #define CONFIG_SYS_I2C_FSL
548 #define CONFIG_SYS_FSL_I2C_SPEED 400000
549 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
550 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
551 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
552 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
553 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
554 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
555 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
556 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
561 #undef CONFIG_ID_EEPROM
563 #define CONFIG_RTC_PT7C4338
564 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
565 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
567 /* enable read and write access to EEPROM */
568 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
569 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
570 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
572 #if defined(CONFIG_PCI)
575 * Memory space is mapped 1-1, but I/O space must start from 0.
578 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
579 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
580 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
581 #ifdef CONFIG_PHYS_64BIT
582 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
583 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
585 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
586 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
588 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
589 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
590 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
591 #ifdef CONFIG_PHYS_64BIT
592 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
594 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
596 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
598 /* controller 1, Slot 2, tgtid 1, Base address a000 */
599 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
600 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
601 #ifdef CONFIG_PHYS_64BIT
602 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
603 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
605 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
606 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
608 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
609 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
610 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
611 #ifdef CONFIG_PHYS_64BIT
612 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
614 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
616 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
618 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
619 #endif /* CONFIG_PCI */
621 #if defined(CONFIG_TSEC_ENET)
623 #define CONFIG_TSEC1_NAME "eTSEC1"
625 #define CONFIG_TSEC2_NAME "eTSEC2"
627 #define CONFIG_TSEC3_NAME "eTSEC3"
629 #define TSEC1_PHY_ADDR 2
630 #define TSEC2_PHY_ADDR 0
631 #define TSEC3_PHY_ADDR 1
633 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
634 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
635 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
637 #define TSEC1_PHYIDX 0
638 #define TSEC2_PHYIDX 0
639 #define TSEC3_PHYIDX 0
641 #define CONFIG_ETHPRIME "eTSEC1"
643 #define CONFIG_HAS_ETH0
644 #define CONFIG_HAS_ETH1
645 #define CONFIG_HAS_ETH2
646 #endif /* CONFIG_TSEC_ENET */
649 /* QE microcode/firmware address */
650 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
651 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
652 #endif /* CONFIG_QE */
654 #ifdef CONFIG_TARGET_P1025RDB
656 * QE UEC ethernet configuration
658 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
660 #undef CONFIG_UEC_ETH
661 #define CONFIG_PHY_MODE_NEED_CHANGE
663 #define CONFIG_UEC_ETH1 /* ETH1 */
664 #define CONFIG_HAS_ETH0
666 #ifdef CONFIG_UEC_ETH1
667 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
668 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
669 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
670 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
671 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
672 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
673 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
674 #endif /* CONFIG_UEC_ETH1 */
676 #define CONFIG_UEC_ETH5 /* ETH5 */
677 #define CONFIG_HAS_ETH1
679 #ifdef CONFIG_UEC_ETH5
680 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
681 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
682 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
683 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
684 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
685 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
686 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
687 #endif /* CONFIG_UEC_ETH5 */
688 #endif /* CONFIG_TARGET_P1025RDB */
693 #ifdef CONFIG_SPIFLASH
694 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
695 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
696 #define CONFIG_ENV_SECT_SIZE 0x10000
697 #elif defined(CONFIG_SDCARD)
698 #define CONFIG_FSL_FIXED_MMC_LOCATION
699 #define CONFIG_ENV_SIZE 0x2000
700 #define CONFIG_SYS_MMC_ENV_DEV 0
701 #elif defined(CONFIG_NAND)
702 #ifdef CONFIG_TPL_BUILD
703 #define CONFIG_ENV_SIZE 0x2000
704 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
706 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
708 #define CONFIG_ENV_OFFSET (1024 * 1024)
709 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
710 #elif defined(CONFIG_SYS_RAMBOOT)
711 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
712 #define CONFIG_ENV_SIZE 0x2000
714 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
715 #define CONFIG_ENV_SIZE 0x2000
716 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
719 #define CONFIG_LOADS_ECHO /* echo on for serial download */
720 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
725 #define CONFIG_HAS_FSL_DR_USB
727 #if defined(CONFIG_HAS_FSL_DR_USB)
728 #ifdef CONFIG_USB_EHCI_HCD
729 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
730 #define CONFIG_USB_EHCI_FSL
734 #if defined(CONFIG_TARGET_P1020RDB_PD)
735 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
739 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
742 #undef CONFIG_WATCHDOG /* watchdog disabled */
745 * Miscellaneous configurable options
747 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
750 * For booting Linux, the board info and command line data
751 * have to be in the first 64 MB of memory, since this is
752 * the maximum mapped by the Linux kernel during initialization.
754 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
755 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
757 #if defined(CONFIG_CMD_KGDB)
758 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
762 * Environment Configuration
764 #define CONFIG_HOSTNAME "unknown"
765 #define CONFIG_ROOTPATH "/opt/nfsroot"
766 #define CONFIG_BOOTFILE "uImage"
767 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
769 /* default location for tftp and bootm */
770 #define CONFIG_LOADADDR 1000000
773 #define __NOR_RST_CMD \
774 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
775 i2c mw 18 3 __SW_BOOT_MASK 1; reset
778 #define __SPI_RST_CMD \
779 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
780 i2c mw 18 3 __SW_BOOT_MASK 1; reset
783 #define __SD_RST_CMD \
784 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
785 i2c mw 18 3 __SW_BOOT_MASK 1; reset
787 #ifdef __SW_BOOT_NAND
788 #define __NAND_RST_CMD \
789 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
790 i2c mw 18 3 __SW_BOOT_MASK 1; reset
792 #ifdef __SW_BOOT_PCIE
793 #define __PCIE_RST_CMD \
794 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
795 i2c mw 18 3 __SW_BOOT_MASK 1; reset
798 #define CONFIG_EXTRA_ENV_SETTINGS \
800 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
801 "loadaddr=1000000\0" \
802 "bootfile=uImage\0" \
803 "tftpflash=tftpboot $loadaddr $uboot; " \
804 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
805 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
806 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
807 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
808 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
809 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
810 "consoledev=ttyS0\0" \
811 "ramdiskaddr=2000000\0" \
812 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
813 "fdtaddr=1e00000\0" \
815 "jffs2nor=mtdblock3\0" \
816 "norbootaddr=ef080000\0" \
817 "norfdtaddr=ef040000\0" \
818 "jffs2nand=mtdblock9\0" \
819 "nandbootaddr=100000\0" \
820 "nandfdtaddr=80000\0" \
821 "ramdisk_size=120000\0" \
822 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
823 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
824 __stringify(__NOR_RST_CMD)"\0" \
825 __stringify(__SPI_RST_CMD)"\0" \
826 __stringify(__SD_RST_CMD)"\0" \
827 __stringify(__NAND_RST_CMD)"\0" \
828 __stringify(__PCIE_RST_CMD)"\0"
830 #define CONFIG_NFSBOOTCOMMAND \
831 "setenv bootargs root=/dev/nfs rw " \
832 "nfsroot=$serverip:$rootpath " \
833 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
834 "console=$consoledev,$baudrate $othbootargs;" \
835 "tftp $loadaddr $bootfile;" \
836 "tftp $fdtaddr $fdtfile;" \
837 "bootm $loadaddr - $fdtaddr"
839 #define CONFIG_HDBOOT \
840 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
841 "console=$consoledev,$baudrate $othbootargs;" \
843 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
844 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
845 "bootm $loadaddr - $fdtaddr"
847 #define CONFIG_USB_FAT_BOOT \
848 "setenv bootargs root=/dev/ram rw " \
849 "console=$consoledev,$baudrate $othbootargs " \
850 "ramdisk_size=$ramdisk_size;" \
852 "fatload usb 0:2 $loadaddr $bootfile;" \
853 "fatload usb 0:2 $fdtaddr $fdtfile;" \
854 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
855 "bootm $loadaddr $ramdiskaddr $fdtaddr"
857 #define CONFIG_USB_EXT2_BOOT \
858 "setenv bootargs root=/dev/ram rw " \
859 "console=$consoledev,$baudrate $othbootargs " \
860 "ramdisk_size=$ramdisk_size;" \
862 "ext2load usb 0:4 $loadaddr $bootfile;" \
863 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
864 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
865 "bootm $loadaddr $ramdiskaddr $fdtaddr"
867 #define CONFIG_NORBOOT \
868 "setenv bootargs root=/dev/$jffs2nor rw " \
869 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
870 "bootm $norbootaddr - $norfdtaddr"
872 #define CONFIG_RAMBOOTCOMMAND \
873 "setenv bootargs root=/dev/ram rw " \
874 "console=$consoledev,$baudrate $othbootargs " \
875 "ramdisk_size=$ramdisk_size;" \
876 "tftp $ramdiskaddr $ramdiskfile;" \
877 "tftp $loadaddr $bootfile;" \
878 "tftp $fdtaddr $fdtfile;" \
879 "bootm $loadaddr $ramdiskaddr $fdtaddr"
881 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
883 #endif /* __CONFIG_H */