2 * Common configuration options for ifm camera boards
5 * Sebastien Cazaux, ifm electronic gmbh
8 * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
10 * SPDX-License-Identifier: GPL-2.0+
13 #ifndef __O2D_CONFIG_H
14 #define __O2D_CONFIG_H
17 * High Level Configuration Options
19 #define CONFIG_MPC5200
21 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */
23 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
24 #if defined(CONFIG_CMD_KGDB)
25 /* log base 2 of the above value */
26 #define CONFIG_SYS_CACHELINE_SHIFT 5
30 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
35 /* preserve space for the post_word at end of on-chip SRAM */
36 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
40 * Serial console configuration
42 #define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */
43 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
44 #define CONFIG_SYS_BAUDRATE_TABLE \
45 { 9600, 19200, 38400, 57600, 115200, 230400 }
49 * 0x40000000 - 0x4fffffff - PCI Memory
50 * 0x50000000 - 0x50ffffff - PCI IO Space
52 #define CONFIG_PCI_PNP 1
54 #define CONFIG_PCI_MEM_BUS 0x40000000
55 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
56 #define CONFIG_PCI_MEM_SIZE 0x10000000
58 #define CONFIG_PCI_IO_BUS 0x50000000
59 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
60 #define CONFIG_PCI_IO_SIZE 0x01000000
62 #define CONFIG_SYS_XLB_PIPELINING 1
65 #define CONFIG_MAC_PARTITION
66 #define CONFIG_DOS_PARTITION
67 #define CONFIG_ISO_PARTITION
69 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
71 #define CONFIG_SYS_ALT_MEMTEST /* Much more complex memory test */
76 #define CONFIG_CMD_EEPROM
78 #define CONFIG_CMD_PCI
81 #define CONFIG_CMD_DIAG
84 #if (CONFIG_SYS_TEXT_BASE == 0xFC000000) || (CONFIG_SYS_TEXT_BASE == 0xFF000000)
85 /* Boot low with 16 or 32 MB Flash */
86 #define CONFIG_SYS_LOWBOOT 1
87 #elif (CONFIG_SYS_TEXT_BASE != 0x00100000)
88 #error "CONFIG_SYS_TEXT_BASE value is invalid"
92 #define CONFIG_PREBOOT "run master"
94 #undef CONFIG_BOOTARGS
96 #if !defined(CONSOLE_DEV)
97 #define CONSOLE_DEV "ttyPSC1"
101 * Default environment for booting old and new kernel versions
103 #define CONFIG_IFM_DEFAULT_ENV_OLD \
104 "flash_self_old=run ramargs addip addmem;" \
105 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
106 "flash_nfs_old=run nfsargs addip addmem;" \
107 "bootm ${kernel_addr}\0" \
108 "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
109 "run nfsargs addip addmem;" \
110 "bootm ${kernel_addr_r}\0"
112 #define CONFIG_IFM_DEFAULT_ENV_NEW \
113 "fdt_addr_r=900000\0" \
114 "fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0" \
115 "flash_self=run ramargs addip addtty addmisc;" \
116 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
117 "flash_nfs=run nfsargs addip addtty addmisc;" \
118 "bootm ${kernel_addr} - ${fdt_addr}\0" \
119 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
120 "tftp ${fdt_addr_r} ${fdt_file}; " \
121 "run nfsargs addip addtty addmisc;" \
122 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
124 #define CONFIG_IFM_DEFAULT_ENV_SETTINGS \
126 "addip=setenv bootargs ${bootargs} " \
127 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
128 ":${hostname}:${netdev}:off panic=1\0" \
129 "addmem=setenv bootargs ${bootargs} ${memlimit}\0" \
130 "addmisc=sete bootargs ${bootargs} ${miscargs}\0" \
131 "addtty=sete bootargs ${bootargs} console=" \
132 CONSOLE_DEV ",${baudrate}\0" \
133 "bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0" \
134 "kernel_addr_r=600000\0" \
135 "initrd_high=0x03e00000\0" \
136 "memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0" \
137 "memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \
139 "nfsargs=setenv bootargs root=/dev/nfs rw " \
140 "nfsroot=${serverip}:${rootpath}\0" \
141 "ramargs=setenv bootargs root=/dev/ram rw\0" \
142 "linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\
143 "progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \
144 "cp.b ${fileaddr} ${linbot} ${filesize}\0" \
145 "ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\
146 "progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};" \
147 "cp.b ${fileaddr} ${rambot} ${filesize}\0" \
148 "jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0" \
149 "progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};" \
150 "cp.b ${fileaddr} ${jffbot} ${filesize}\0" \
151 "rootpath=/opt/eldk/ppc_6xx\0" \
152 "uboname=" CONFIG_BOARD_NAME \
153 "/u-boot.bin_" CONFIG_BOARD_NAME "_act\0" \
154 "progubo=tftp 200000 ${uboname};" \
155 "protect off ${ubobot} ${ubotop};" \
156 "erase ${ubobot} ${ubotop};" \
157 "cp.b ${fileaddr} ${ubobot} ${filesize}\0" \
159 "post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;" \
160 "setenv bootdelay 1;" \
161 "crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" " \
162 BOARD_POST_CRC32_END";" \
163 "setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0"
165 #define CONFIG_BOOTCOMMAND "run post"
168 * IPB Bus clocking configuration.
170 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
172 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
174 * PCI Bus clocking configuration
176 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
177 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
178 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
180 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
186 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
187 #define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
188 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
189 #define CONFIG_SYS_I2C_SLAVE 0x7F
192 * EEPROM configuration:
194 * O2DNT board is equiped with Ramtron FRAM device FM24CL16
195 * 16 Kib Ferroelectric Nonvolatile serial RAM memory
196 * organized as 2048 x 8 bits and addressable as eight I2C devices
197 * 0x50 ... 0x57 each 256 bytes in size
200 #define CONFIG_SYS_I2C_FRAM
201 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
202 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
203 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
205 * There is no write delay with FRAM, write operations are performed at bus
206 * speed. Thus, no status polling or write delay is needed.
210 * Flash configuration
212 #define CONFIG_SYS_FLASH_CFI 1
213 #define CONFIG_FLASH_CFI_DRIVER 1
214 #define CONFIG_FLASH_16BIT
215 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
216 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
217 #define CONFIG_SYS_FLASH_EMPTY_INFO
219 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
220 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
221 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Erase Timeout (in ms) */
222 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (in ms) */
223 /* Timeout for Flash Clear Lock Bits (in ms) */
224 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
225 /* "Real" (hardware) sectors protection */
226 #define CONFIG_SYS_FLASH_PROTECTION
229 * Environment settings
231 #define CONFIG_ENV_IS_IN_FLASH 1
232 #define CONFIG_ENV_SIZE 0x20000
233 #define CONFIG_ENV_SECT_SIZE 0x20000
234 #define CONFIG_ENV_OVERWRITE 1
235 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
240 #define CONFIG_SYS_MBAR 0xF0000000
241 #define CONFIG_SYS_SDRAM_BASE 0x00000000
242 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
244 /* Use SRAM until RAM will be available */
245 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
247 /* preserve space for the post_word at end of on-chip SRAM */
248 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
250 /* End of used area in DPRAM */
251 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
254 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
255 GENERATED_GBL_DATA_SIZE)
256 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
258 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
259 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* 192 kB for Monitor */
260 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128 kB for malloc() */
261 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial map for Linux */
263 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
264 #define CONFIG_SYS_RAMBOOT 1
268 * Ethernet configuration
270 #define CONFIG_MPC5xxx_FEC
271 #define CONFIG_MPC5xxx_FEC_MII100
272 #define CONFIG_PHY_ADDR 0x00
273 #define CONFIG_RESET_PHY_R
278 #define CONFIG_SYS_GPIO_DATADIR 0x00000064 /* PSC1_2, PSC2_1,2 output */
279 #define CONFIG_SYS_GPIO_OPENDRAIN 0x00000000 /* No open drain */
280 #define CONFIG_SYS_GPIO_DATAVALUE 0x00000000 /* PSC1_1 to 1, rest to 0 */
281 #define CONFIG_SYS_GPIO_ENABLE 0x00000064 /* PSC1_2, PSC2_1,2 enable */
284 * Miscellaneous configurable options
286 #define CONFIG_SYS_LONGHELP /* undef to save memory */
287 #define CONFIG_CMDLINE_EDITING
289 #if defined(CONFIG_CMD_KGDB)
290 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
292 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
294 /* Print Buffer Size */
295 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
296 sizeof(CONFIG_SYS_PROMPT) + 16)
297 /* max number of command args */
298 #define CONFIG_SYS_MAXARGS 16
299 /* Boot Argument Buffer Size */
300 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
302 /* default load address */
303 #define CONFIG_SYS_LOAD_ADDR 0x100000
305 /* decrementer freq: 1 ms ticks */
308 * Various low-level settings
310 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
311 #define CONFIG_SYS_HID0_FINAL HID0_ICE
313 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
314 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
315 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
316 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
318 #define CONFIG_BOARD_EARLY_INIT_R
320 #define CONFIG_SYS_CS_BURST 0x00000000
321 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
326 #define OF_CPU "PowerPC,5200@0"
327 #define OF_SOC "soc5200@f0000000"
328 #define OF_TBCLK (bd->bi_busfreq / 4)
330 #endif /* __O2D_CONFIG_H */