2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 * Configuration settings for the MX51EVK Board
8 * SPDX-License-Identifier: GPL-2.0+
14 /* High Level Configuration Options */
16 #define CONFIG_SYS_FSL_CLK
17 #define CONFIG_SYS_TEXT_BASE 0x97800000
19 #include <asm/arch/imx-regs.h>
21 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
22 #define CONFIG_SETUP_MEMORY_TAGS
23 #define CONFIG_INITRD_TAG
24 #define CONFIG_REVISION_TAG
26 #define CONFIG_MACH_TYPE MACH_TYPE_MX51_BABBAGE
28 * Size of malloc() pool
30 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
35 #define CONFIG_FSL_IIM
37 #define CONFIG_MXC_UART
38 #define CONFIG_MXC_UART_BASE UART1_BASE
39 #define CONFIG_MXC_GPIO
45 #define CONFIG_MXC_SPI
49 #define CONFIG_POWER_SPI
50 #define CONFIG_POWER_FSL
51 #define CONFIG_FSL_PMIC_BUS 0
52 #define CONFIG_FSL_PMIC_CS 0
53 #define CONFIG_FSL_PMIC_CLK 2500000
54 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
55 #define CONFIG_FSL_PMIC_BITLEN 32
56 #define CONFIG_RTC_MC13XXX
61 #define CONFIG_FSL_ESDHC
62 #define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
63 #define CONFIG_SYS_FSL_ESDHC_NUM 2
70 #define CONFIG_FEC_MXC
71 #define IMX_FEC_BASE FEC_BASE_ADDR
72 #define CONFIG_FEC_MXC_PHYADDR 0x1F
75 #define CONFIG_USB_EHCI_MX5
76 #define CONFIG_MXC_USB_PORT 1
77 #define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI
78 #define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
80 /* Framebuffer and LCD */
81 #define CONFIG_PREBOOT
82 #define CONFIG_VIDEO_IPUV3
83 #define CONFIG_VIDEO_BMP_RLE8
84 #define CONFIG_SPLASH_SCREEN
85 #define CONFIG_BMP_16BPP
86 #define CONFIG_VIDEO_LOGO
87 #define CONFIG_IPUV3_CLK 133000000
89 /* allow to overwrite serial and ethaddr */
90 #define CONFIG_ENV_OVERWRITE
91 #define CONFIG_CONS_INDEX 1
93 #define CONFIG_ETHPRIME "FEC0"
95 #define CONFIG_LOADADDR 0x92000000 /* loadaddr env var */
97 #define CONFIG_EXTRA_ENV_SETTINGS \
100 "fdt_file=imx51-babbage.dtb\0" \
101 "fdt_addr=0x91000000\0" \
106 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
107 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
108 "root=${mmcroot}\0" \
110 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
111 "bootscript=echo Running bootscript from mmc ...; " \
113 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
114 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
115 "mmcboot=echo Booting from mmc ...; " \
117 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
118 "if run loadfdt; then " \
119 "bootz ${loadaddr} - ${fdt_addr}; " \
121 "if test ${boot_fdt} = try; then " \
124 "echo WARN: Cannot load the DT; " \
130 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
132 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
133 "netboot=echo Booting from net ...; " \
135 "if test ${ip_dyn} = yes; then " \
136 "setenv get_cmd dhcp; " \
138 "setenv get_cmd tftp; " \
140 "${get_cmd} ${image}; " \
141 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
142 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
143 "bootz ${loadaddr} - ${fdt_addr}; " \
145 "if test ${boot_fdt} = try; then " \
148 "echo ERROR: Cannot load the DT; " \
156 #define CONFIG_BOOTCOMMAND \
157 "mmc dev ${mmcdev}; if mmc rescan; then " \
158 "if run loadbootscript; then " \
161 "if run loadimage; then " \
163 "else run netboot; " \
166 "else run netboot; fi"
168 #define CONFIG_ARP_TIMEOUT 200UL
171 * Miscellaneous configurable options
173 #define CONFIG_SYS_LONGHELP /* undef to save memory */
174 #define CONFIG_AUTO_COMPLETE
176 #define CONFIG_SYS_MEMTEST_START 0x90000000
177 #define CONFIG_SYS_MEMTEST_END 0x90010000
179 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
181 #define CONFIG_CMDLINE_EDITING
183 /*-----------------------------------------------------------------------
184 * Physical Memory Map
186 #define CONFIG_NR_DRAM_BANKS 1
187 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
188 #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
190 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
191 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
192 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
194 #define CONFIG_SYS_INIT_SP_OFFSET \
195 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
196 #define CONFIG_SYS_INIT_SP_ADDR \
197 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
199 #define CONFIG_SYS_DDR_CLKSEL 0
200 #define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
201 #define CONFIG_SYS_MAIN_PWR_ON
203 /*-----------------------------------------------------------------------
204 * environment organization
206 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
207 #define CONFIG_ENV_SIZE (8 * 1024)
208 #define CONFIG_SYS_MMC_ENV_DEV 0