include/configs/mpc8308_p1m.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15
  16 /*
  17  * On-board devices
  18  *
  19  * TSECs
  20  */
  21 #define CONFIG_TSEC1
  22 #define CONFIG_TSEC2
  23
  24 /*
  25  * Hardware Reset Configuration Word
  26  * if CLKIN is 66.66MHz, then
  27  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  28  * We choose the A type silicon as default, so the core is 400Mhz.
  29  */
  30 #define CONFIG_SYS_HRCW_LOW (\
  31         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  32         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  33         HRCWL_SVCOD_DIV_2 |\
  34         HRCWL_CSB_TO_CLKIN_4X1 |\
  35         HRCWL_CORE_TO_CSB_3X1)
  36 /*
  37  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  38  * in 8308's HRCWH according to the manual, but original Freescale's
  39  * code has them and I've expirienced some problems using the board
  40  * with BDI3000 attached when I've tried to set these bits to zero
  41  * (UART doesn't work after the 'reset run' command).
  42  */
  43 #define CONFIG_SYS_HRCW_HIGH (\
  44         HRCWH_PCI_HOST |\
  45         HRCWH_PCI1_ARBITER_ENABLE |\
  46         HRCWH_CORE_ENABLE |\
  47         HRCWH_FROM_0X00000100 |\
  48         HRCWH_BOOTSEQ_DISABLE |\
  49         HRCWH_SW_WATCHDOG_DISABLE |\
  50         HRCWH_ROM_LOC_LOCAL_16BIT |\
  51         HRCWH_RL_EXT_LEGACY |\
  52         HRCWH_TSEC1M_IN_MII |\
  53         HRCWH_TSEC2M_IN_MII |\
  54         HRCWH_BIG_ENDIAN)
  55
  56 /*
  57  * System IO Config
  58  */
  59 #define CONFIG_SYS_SICRH (\
  60         SICRH_ESDHC_A_GPIO |\
  61         SICRH_ESDHC_B_GPIO |\
  62         SICRH_ESDHC_C_GTM |\
  63         SICRH_GPIO_A_TSEC2 |\
  64         SICRH_GPIO_B_TSEC2_TX_CLK |\
  65         SICRH_IEEE1588_A_GPIO |\
  66         SICRH_USB |\
  67         SICRH_GTM_GPIO |\
  68         SICRH_IEEE1588_B_GPIO |\
  69         SICRH_ETSEC2_CRS |\
  70         SICRH_GPIOSEL_1 |\
  71         SICRH_TMROBI_V3P3 |\
  72         SICRH_TSOBI1_V3P3 |\
  73         SICRH_TSOBI2_V3P3)      /* 0xf577d100 */
  74 #define CONFIG_SYS_SICRL (\
  75         SICRL_SPI_PF0 |\
  76         SICRL_UART_PF0 |\
  77         SICRL_IRQ_PF0 |\
  78         SICRL_I2C2_PF0 |\
  79         SICRL_ETSEC1_TX_CLK)    /* 0x00000000 */
  80
  81 #define CONFIG_SYS_GPIO1_PRELIM
  82 /* GPIO Default input/output settings */
  83 #define CONFIG_SYS_GPIO1_DIR        0x7AAF8C00
  84 /*
  85  * Default GPIO values:
  86  * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
  87  */
  88 #define CONFIG_SYS_GPIO1_DAT        0x08008C00
  89
  90 /*
  91  * IMMR new address
  92  */
  93 #define CONFIG_SYS_IMMR         0xE0000000
  94
  95 /*
  96  * SERDES
  97  */
  98 #define CONFIG_FSL_SERDES
  99 #define CONFIG_FSL_SERDES1      0xe3000
 100
 101 /*
 102  * Arbiter Setup
 103  */
 104 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
 105 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
 106 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
 107
 108 /*
 109  * DDR Setup
 110  */
 111 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 112 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 113 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 114 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 115 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 116                                 | DDRCDR_PZ_LOZ \
 117                                 | DDRCDR_NZ_LOZ \
 118                                 | DDRCDR_ODT \
 119                                 | DDRCDR_Q_DRN)
 120                                 /* 0x7b880001 */
 121 /*
 122  * Manually set up DDR parameters
 123  * consist of two chips HY5PS12621BFP-C4 from HYNIX
 124  */
 125
 126 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 127
 128 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 129 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 130                                         | CSCONFIG_ODT_RD_NEVER \
 131                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
 132                                         | CSCONFIG_ROW_BIT_13 \
 133                                         | CSCONFIG_COL_BIT_10)
 134                                         /* 0x80010102 */
 135 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 136 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 137                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 138                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 139                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 140                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 141                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 142                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 143                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 144                                 /* 0x00220802 */
 145 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 146                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 147                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 148                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 149                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
 150                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 151                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 152                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 153                                 /* 0x27256222 */
 154 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 155                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 156                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 157                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 158                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 159                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 160                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 161                                 /* 0x121048c5 */
 162 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 163                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 164                                 /* 0x03600100 */
 165 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 166                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 167                                 | SDRAM_CFG_DBW_32)
 168                                 /* 0x43080000 */
 169
 170 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 171 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 172                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 173                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 174 #define CONFIG_SYS_DDR_MODE2            0x00000000
 175
 176 /*
 177  * Memory test
 178  */
 179 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 180 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 181
 182 /*
 183  * The reserved memory
 184  */
 185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 186
 187 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 188 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 189
 190 /*
 191  * Initial RAM Base Address Setup
 192  */
 193 #define CONFIG_SYS_INIT_RAM_LOCK        1
 194 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 195 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 196 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 197         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 198
 199 /*
 200  * Local Bus Configuration & Clock Setup
 201  */
 202 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 203 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 204 #define CONFIG_SYS_LBC_LBCR             0x00040000
 205
 206 /*
 207  * FLASH on the Local Bus
 208  */
 209 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 210
 211 #define CONFIG_SYS_FLASH_BASE           0xFC000000 /* FLASH base address */
 212 #define CONFIG_SYS_FLASH_SIZE           64 /* FLASH size is 64M */
 213
 214 /* Window base at flash base */
 215 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 216 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 217
 218 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 219                                 | BR_PS_16      /* 16 bit port */ \
 220                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 221                                 | BR_V)         /* valid */
 222 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 223                                 | OR_UPM_XAM \
 224                                 | OR_GPCM_CSNT \
 225                                 | OR_GPCM_ACS_DIV2 \
 226                                 | OR_GPCM_XACS \
 227                                 | OR_GPCM_SCY_4 \
 228                                 | OR_GPCM_TRLX_SET \
 229                                 | OR_GPCM_EHTR_SET)
 230
 231 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 232 #define CONFIG_SYS_MAX_FLASH_SECT       512
 233
 234 /* Flash Erase Timeout (ms) */
 235 #define CONFIG_SYS_FLASH_ERASE_TOUT     (1000 * 1024)
 236 /* Flash Write Timeout (ms) */
 237 #define CONFIG_SYS_FLASH_WRITE_TOUT     (500 * 1024)
 238
 239 /*
 240  * SJA1000 CAN controller on Local Bus
 241  */
 242 #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
 243 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_SJA1000_BASE \
 244                                 | BR_PS_8       /* 8 bit port size */ \
 245                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 246                                 | BR_V)         /* valid */
 247 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
 248                                 | OR_GPCM_SCY_5 \
 249                                 | OR_GPCM_EHTR_SET)
 250                                 /* 0xFFFF8052 */
 251
 252 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_SJA1000_BASE
 253 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 254
 255 /*
 256  * CPLD on Local Bus
 257  */
 258 #define CONFIG_SYS_CPLD_BASE    0xFBFF8000
 259 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_CPLD_BASE \
 260                                 | BR_PS_8       /* 8 bit port */ \
 261                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 262                                 | BR_V)         /* valid */
 263 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB \
 264                                 | OR_GPCM_SCY_4 \
 265                                 | OR_GPCM_EHTR_SET)
 266                                 /* 0xFFFF8042 */
 267
 268 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_CPLD_BASE
 269 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 270
 271 /*
 272  * Serial Port
 273  */
 274 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 275 #define CONFIG_SYS_NS16550_SERIAL
 276 #define CONFIG_SYS_NS16550_REG_SIZE     1
 277 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 278
 279 #define CONFIG_SYS_BAUDRATE_TABLE  \
 280         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 281
 282 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 283 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 284
 285 /* I2C */
 286 #define CONFIG_SYS_I2C
 287 #define CONFIG_SYS_I2C_FSL
 288 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 289 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 290 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 291 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 292 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 293 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 294
 295 /*
 296  * General PCI
 297  * Addresses are mapped 1-1.
 298  */
 299 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 300 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 301 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 302 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 303 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 304 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 305 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 306 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 307 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 308
 309 /* enable PCIE clock */
 310 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 311
 312 #define CONFIG_PCI_INDIRECT_BRIDGE
 313 #define CONFIG_PCIE
 314
 315 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 316 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 317
 318 /*
 319  * TSEC
 320  */
 321 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 322 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 323 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 324 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 325
 326 /*
 327  * TSEC ethernet configuration
 328  */
 329 #define CONFIG_TSEC1_NAME       "eTSEC0"
 330 #define CONFIG_TSEC2_NAME       "eTSEC1"
 331 #define TSEC1_PHY_ADDR          1
 332 #define TSEC2_PHY_ADDR          2
 333 #define TSEC1_PHYIDX            0
 334 #define TSEC2_PHYIDX            0
 335 #define TSEC1_FLAGS             0
 336 #define TSEC2_FLAGS             0
 337
 338 /* Options are: eTSEC[0-1] */
 339 #define CONFIG_ETHPRIME         "eTSEC0"
 340
 341 /*
 342  * Environment
 343  */
 344 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 345                                  CONFIG_SYS_MONITOR_LEN)
 346 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 347 #define CONFIG_ENV_SIZE         0x2000
 348 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 349 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 350
 351 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 352 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 353
 354 /*
 355  * BOOTP options
 356  */
 357 #define CONFIG_BOOTP_BOOTFILESIZE
 358
 359 /*
 360  * Command line configuration.
 361  */
 362
 363 /*
 364  * Miscellaneous configurable options
 365  */
 366 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 367
 368 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 369
 370 /* Boot Argument Buffer Size */
 371 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 372
 373 /*
 374  * For booting Linux, the board info and command line data
 375  * have to be in the first 8 MB of memory, since this is
 376  * the maximum mapped by the Linux kernel during initialization.
 377  */
 378 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 379
 380 /*
 381  * Core HID Setup
 382  */
 383 #define CONFIG_SYS_HID0_INIT    0x000000000
 384 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 385                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 386                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 387 #define CONFIG_SYS_HID2         HID2_HBE
 388
 389 /*
 390  * MMU Setup
 391  */
 392
 393 /* DDR: cache cacheable */
 394 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 395                                         BATL_MEMCOHERENCE)
 396 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
 397                                         BATU_VS | BATU_VP)
 398 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 399 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 400
 401 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 402 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 403                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 404 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
 405                                         BATU_VP)
 406 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 407 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 408
 409 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 410 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 411                                         BATL_MEMCOHERENCE)
 412 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
 413                                         BATU_VS | BATU_VP)
 414 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 415                                         BATL_CACHEINHIBIT | \
 416                                         BATL_GUARDEDSTORAGE)
 417 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 418
 419 /* Stack in dcache: cacheable, no memory coherence */
 420 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 421 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 422                                         BATU_VS | BATU_VP)
 423 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 424 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 425
 426 /*
 427  * Environment Configuration
 428  */
 429
 430 #define CONFIG_ENV_OVERWRITE
 431
 432 #if defined(CONFIG_TSEC_ENET)
 433 #define CONFIG_HAS_ETH0
 434 #define CONFIG_HAS_ETH1
 435 #endif
 436
 437 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 438
 439
 440 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 441         "netdev=eth0\0"                                                 \
 442         "consoledev=ttyS0\0"                                            \
 443         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 444                 "nfsroot=${serverip}:${rootpath}\0"                     \
 445         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 446         "addip=setenv bootargs ${bootargs} "                            \
 447                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 448                 ":${hostname}:${netdev}:off panic=1\0"                  \
 449         "addtty=setenv bootargs ${bootargs}"                            \
 450                 " console=${consoledev},${baudrate}\0"                  \
 451         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 452         "addmisc=setenv bootargs ${bootargs}\0"                         \
 453         "kernel_addr=FC0A0000\0"                                        \
 454         "fdt_addr=FC2A0000\0"                                           \
 455         "ramdisk_addr=FC2C0000\0"                                       \
 456         "u-boot=mpc8308_p1m/u-boot.bin\0"                               \
 457         "kernel_addr_r=1000000\0"                                       \
 458         "fdt_addr_r=C00000\0"                                           \
 459         "hostname=mpc8308_p1m\0"                                        \
 460         "bootfile=mpc8308_p1m/uImage\0"                                 \
 461         "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0"                         \
 462         "rootpath=/opt/eldk-4.2/ppc_6xx\0"                              \
 463         "flash_self=run ramargs addip addtty addmtd addmisc;"           \
 464                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 465         "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
 466                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 467         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 468                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 469                 "run nfsargs addip addtty addmtd addmisc;"              \
 470                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 471         "bootcmd=run flash_self\0"                                      \
 472         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 473         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 474                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 475                 " +${filesize};cp.b ${fileaddr} "                       \
 476                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 477         "upd=run load update\0"                                         \
 478
 479 #endif  /* __CONFIG_H */