1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
27 #define CONFIG_SYS_SICRH (\
32 SICRH_GPIO_B_TSEC2_TX_CLK |\
33 SICRH_IEEE1588_A_GPIO |\
36 SICRH_IEEE1588_B_GPIO |\
41 SICRH_TSOBI2_V3P3) /* 0xf577d100 */
42 #define CONFIG_SYS_SICRL (\
47 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
49 #define CONFIG_SYS_GPIO1_PRELIM
50 /* GPIO Default input/output settings */
51 #define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00
53 * Default GPIO values:
54 * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
56 #define CONFIG_SYS_GPIO1_DAT 0x08008C00
61 #define CONFIG_SYS_IMMR 0xE0000000
66 #define CONFIG_FSL_SERDES
67 #define CONFIG_FSL_SERDES1 0xe3000
72 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
73 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
74 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
79 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
80 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
81 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
82 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
83 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
90 * Manually set up DDR parameters
91 * consist of two chips HY5PS12621BFP-C4 from HYNIX
94 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
96 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
97 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
98 | CSCONFIG_ODT_RD_NEVER \
99 | CSCONFIG_ODT_WR_ONLY_CURRENT \
100 | CSCONFIG_ROW_BIT_13 \
101 | CSCONFIG_COL_BIT_10)
103 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
104 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
105 | (0 << TIMING_CFG0_WRT_SHIFT) \
106 | (0 << TIMING_CFG0_RRT_SHIFT) \
107 | (0 << TIMING_CFG0_WWT_SHIFT) \
108 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
109 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
110 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
111 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
113 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
114 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
115 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
116 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
117 | (6 << TIMING_CFG1_REFREC_SHIFT) \
118 | (2 << TIMING_CFG1_WRREC_SHIFT) \
119 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
120 | (2 << TIMING_CFG1_WRTORD_SHIFT))
122 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
123 | (4 << TIMING_CFG2_CPO_SHIFT) \
124 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
125 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
126 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
127 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
128 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
130 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
131 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
133 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
134 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
138 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
139 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
140 | (0x0232 << SDRAM_MODE_SD_SHIFT))
141 /* ODT 150ohm CL=3, AL=1 on SDRAM */
142 #define CONFIG_SYS_DDR_MODE2 0x00000000
147 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
148 #define CONFIG_SYS_MEMTEST_END 0x07f00000
151 * The reserved memory
153 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
155 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
156 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
159 * Initial RAM Base Address Setup
161 #define CONFIG_SYS_INIT_RAM_LOCK 1
162 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
163 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
164 #define CONFIG_SYS_GBL_DATA_OFFSET \
165 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
168 * Local Bus Configuration & Clock Setup
170 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
171 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
172 #define CONFIG_SYS_LBC_LBCR 0x00040000
175 * FLASH on the Local Bus
177 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
179 #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */
180 #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */
183 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
184 #define CONFIG_SYS_MAX_FLASH_SECT 512
186 /* Flash Erase Timeout (ms) */
187 #define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024)
188 /* Flash Write Timeout (ms) */
189 #define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024)
192 * SJA1000 CAN controller on Local Bus
194 #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
200 #define CONFIG_SYS_CPLD_BASE 0xFBFF8000
206 #undef CONFIG_SERIAL_SOFTWARE_FIFO
207 #define CONFIG_SYS_NS16550_SERIAL
208 #define CONFIG_SYS_NS16550_REG_SIZE 1
209 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
211 #define CONFIG_SYS_BAUDRATE_TABLE \
212 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
214 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
215 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
218 #define CONFIG_SYS_I2C
219 #define CONFIG_SYS_I2C_FSL
220 #define CONFIG_SYS_FSL_I2C_SPEED 400000
221 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
222 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
223 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
224 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
225 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
229 * Addresses are mapped 1-1.
231 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
232 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
233 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
234 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
235 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
236 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
237 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
238 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
239 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
241 /* enable PCIE clock */
242 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
244 #define CONFIG_PCI_INDIRECT_BRIDGE
247 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
248 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
253 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
254 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
255 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
256 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
259 * TSEC ethernet configuration
261 #define CONFIG_TSEC1_NAME "eTSEC0"
262 #define CONFIG_TSEC2_NAME "eTSEC1"
263 #define TSEC1_PHY_ADDR 1
264 #define TSEC2_PHY_ADDR 2
265 #define TSEC1_PHYIDX 0
266 #define TSEC2_PHYIDX 0
267 #define TSEC1_FLAGS 0
268 #define TSEC2_FLAGS 0
270 /* Options are: eTSEC[0-1] */
271 #define CONFIG_ETHPRIME "eTSEC0"
276 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
277 CONFIG_SYS_MONITOR_LEN)
278 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
279 #define CONFIG_ENV_SIZE 0x2000
280 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
281 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
283 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
284 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
289 #define CONFIG_BOOTP_BOOTFILESIZE
292 * Command line configuration.
296 * Miscellaneous configurable options
298 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
300 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
302 /* Boot Argument Buffer Size */
303 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
306 * For booting Linux, the board info and command line data
307 * have to be in the first 8 MB of memory, since this is
308 * the maximum mapped by the Linux kernel during initialization.
310 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
313 * Environment Configuration
316 #define CONFIG_ENV_OVERWRITE
318 #if defined(CONFIG_TSEC_ENET)
319 #define CONFIG_HAS_ETH0
320 #define CONFIG_HAS_ETH1
323 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
326 #define CONFIG_EXTRA_ENV_SETTINGS \
328 "consoledev=ttyS0\0" \
329 "nfsargs=setenv bootargs root=/dev/nfs rw " \
330 "nfsroot=${serverip}:${rootpath}\0" \
331 "ramargs=setenv bootargs root=/dev/ram rw\0" \
332 "addip=setenv bootargs ${bootargs} " \
333 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
334 ":${hostname}:${netdev}:off panic=1\0" \
335 "addtty=setenv bootargs ${bootargs}" \
336 " console=${consoledev},${baudrate}\0" \
337 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
338 "addmisc=setenv bootargs ${bootargs}\0" \
339 "kernel_addr=FC0A0000\0" \
340 "fdt_addr=FC2A0000\0" \
341 "ramdisk_addr=FC2C0000\0" \
342 "u-boot=mpc8308_p1m/u-boot.bin\0" \
343 "kernel_addr_r=1000000\0" \
344 "fdt_addr_r=C00000\0" \
345 "hostname=mpc8308_p1m\0" \
346 "bootfile=mpc8308_p1m/uImage\0" \
347 "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \
348 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
349 "flash_self=run ramargs addip addtty addmtd addmisc;" \
350 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
351 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
352 "bootm ${kernel_addr} - ${fdt_addr}\0" \
353 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
354 "tftp ${fdt_addr_r} ${fdtfile};" \
355 "run nfsargs addip addtty addmtd addmisc;" \
356 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
357 "bootcmd=run flash_self\0" \
358 "load=tftp ${loadaddr} ${u-boot}\0" \
359 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
360 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
361 " +${filesize};cp.b ${fileaddr} " \
362 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
363 "upd=run load update\0" \
365 #endif /* __CONFIG_H */