include/configs/mpc8308_p1m.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15
  16 /*
  17  * On-board devices
  18  *
  19  * TSECs
  20  */
  21 #define CONFIG_TSEC1
  22 #define CONFIG_TSEC2
  23
  24 #define CONFIG_SYS_GPIO1_PRELIM
  25 /* GPIO Default input/output settings */
  26 #define CONFIG_SYS_GPIO1_DIR        0x7AAF8C00
  27 /*
  28  * Default GPIO values:
  29  * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
  30  */
  31 #define CONFIG_SYS_GPIO1_DAT        0x08008C00
  32
  33 /*
  34  * SERDES
  35  */
  36 #define CONFIG_FSL_SERDES
  37 #define CONFIG_FSL_SERDES1      0xe3000
  38
  39 /*
  40  * Arbiter Setup
  41  */
  42 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  43 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  44 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
  45
  46 /*
  47  * DDR Setup
  48  */
  49 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  50 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  51 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  52 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  53 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  54                                 | DDRCDR_PZ_LOZ \
  55                                 | DDRCDR_NZ_LOZ \
  56                                 | DDRCDR_ODT \
  57                                 | DDRCDR_Q_DRN)
  58                                 /* 0x7b880001 */
  59 /*
  60  * Manually set up DDR parameters
  61  * consist of two chips HY5PS12621BFP-C4 from HYNIX
  62  */
  63
  64 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
  65
  66 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  67 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  68                                         | CSCONFIG_ODT_RD_NEVER \
  69                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
  70                                         | CSCONFIG_ROW_BIT_13 \
  71                                         | CSCONFIG_COL_BIT_10)
  72                                         /* 0x80010102 */
  73 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  74 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  75                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  76                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  77                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  78                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  79                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  80                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  81                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  82                                 /* 0x00220802 */
  83 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  84                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  85                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  86                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  87                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
  88                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  89                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  90                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  91                                 /* 0x27256222 */
  92 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  93                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
  94                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  95                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  96                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  97                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  98                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  99                                 /* 0x121048c5 */
 100 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 101                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 102                                 /* 0x03600100 */
 103 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 104                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 105                                 | SDRAM_CFG_DBW_32)
 106                                 /* 0x43080000 */
 107
 108 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 109 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 110                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 111                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 112 #define CONFIG_SYS_DDR_MODE2            0x00000000
 113
 114 /*
 115  * Memory test
 116  */
 117 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 118 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 119
 120 /*
 121  * The reserved memory
 122  */
 123 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 124
 125 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 126 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 127
 128 /*
 129  * Initial RAM Base Address Setup
 130  */
 131 #define CONFIG_SYS_INIT_RAM_LOCK        1
 132 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 133 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 134 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 135         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 136
 137 /*
 138  * Local Bus Configuration & Clock Setup
 139  */
 140 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 141 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 142 #define CONFIG_SYS_LBC_LBCR             0x00040000
 143
 144 /*
 145  * FLASH on the Local Bus
 146  */
 147 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 148
 149 #define CONFIG_SYS_FLASH_BASE           0xFC000000 /* FLASH base address */
 150 #define CONFIG_SYS_FLASH_SIZE           64 /* FLASH size is 64M */
 151
 152
 153 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 154 #define CONFIG_SYS_MAX_FLASH_SECT       512
 155
 156 /* Flash Erase Timeout (ms) */
 157 #define CONFIG_SYS_FLASH_ERASE_TOUT     (1000 * 1024)
 158 /* Flash Write Timeout (ms) */
 159 #define CONFIG_SYS_FLASH_WRITE_TOUT     (500 * 1024)
 160
 161 /*
 162  * SJA1000 CAN controller on Local Bus
 163  */
 164 #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
 165
 166
 167 /*
 168  * CPLD on Local Bus
 169  */
 170 #define CONFIG_SYS_CPLD_BASE    0xFBFF8000
 171
 172
 173 /*
 174  * Serial Port
 175  */
 176 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 177 #define CONFIG_SYS_NS16550_SERIAL
 178 #define CONFIG_SYS_NS16550_REG_SIZE     1
 179 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 180
 181 #define CONFIG_SYS_BAUDRATE_TABLE  \
 182         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 183
 184 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 185 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 186
 187 /* I2C */
 188 #define CONFIG_SYS_I2C
 189 #define CONFIG_SYS_I2C_FSL
 190 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 191 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 192 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 193 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 194 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 195 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 196
 197 /*
 198  * General PCI
 199  * Addresses are mapped 1-1.
 200  */
 201 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 202 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 203 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 204 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 205 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 206 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 207 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 208 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 209 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 210
 211 /* enable PCIE clock */
 212 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 213
 214 #define CONFIG_PCI_INDIRECT_BRIDGE
 215 #define CONFIG_PCIE
 216
 217 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 218 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 219
 220 /*
 221  * TSEC
 222  */
 223 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 224 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 225 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 226 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 227
 228 /*
 229  * TSEC ethernet configuration
 230  */
 231 #define CONFIG_TSEC1_NAME       "eTSEC0"
 232 #define CONFIG_TSEC2_NAME       "eTSEC1"
 233 #define TSEC1_PHY_ADDR          1
 234 #define TSEC2_PHY_ADDR          2
 235 #define TSEC1_PHYIDX            0
 236 #define TSEC2_PHYIDX            0
 237 #define TSEC1_FLAGS             0
 238 #define TSEC2_FLAGS             0
 239
 240 /* Options are: eTSEC[0-1] */
 241 #define CONFIG_ETHPRIME         "eTSEC0"
 242
 243 /*
 244  * Environment
 245  */
 246 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 247                                  CONFIG_SYS_MONITOR_LEN)
 248 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 249 #define CONFIG_ENV_SIZE         0x2000
 250 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 251 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 252
 253 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 254 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 255
 256 /*
 257  * BOOTP options
 258  */
 259 #define CONFIG_BOOTP_BOOTFILESIZE
 260
 261 /*
 262  * Command line configuration.
 263  */
 264
 265 /*
 266  * Miscellaneous configurable options
 267  */
 268 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 269
 270 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 271
 272 /* Boot Argument Buffer Size */
 273 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 274
 275 /*
 276  * For booting Linux, the board info and command line data
 277  * have to be in the first 8 MB of memory, since this is
 278  * the maximum mapped by the Linux kernel during initialization.
 279  */
 280 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 281
 282 /*
 283  * Environment Configuration
 284  */
 285
 286 #define CONFIG_ENV_OVERWRITE
 287
 288 #if defined(CONFIG_TSEC_ENET)
 289 #define CONFIG_HAS_ETH0
 290 #define CONFIG_HAS_ETH1
 291 #endif
 292
 293 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 294
 295
 296 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 297         "netdev=eth0\0"                                                 \
 298         "consoledev=ttyS0\0"                                            \
 299         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 300                 "nfsroot=${serverip}:${rootpath}\0"                     \
 301         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 302         "addip=setenv bootargs ${bootargs} "                            \
 303                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 304                 ":${hostname}:${netdev}:off panic=1\0"                  \
 305         "addtty=setenv bootargs ${bootargs}"                            \
 306                 " console=${consoledev},${baudrate}\0"                  \
 307         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 308         "addmisc=setenv bootargs ${bootargs}\0"                         \
 309         "kernel_addr=FC0A0000\0"                                        \
 310         "fdt_addr=FC2A0000\0"                                           \
 311         "ramdisk_addr=FC2C0000\0"                                       \
 312         "u-boot=mpc8308_p1m/u-boot.bin\0"                               \
 313         "kernel_addr_r=1000000\0"                                       \
 314         "fdt_addr_r=C00000\0"                                           \
 315         "hostname=mpc8308_p1m\0"                                        \
 316         "bootfile=mpc8308_p1m/uImage\0"                                 \
 317         "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0"                         \
 318         "rootpath=/opt/eldk-4.2/ppc_6xx\0"                              \
 319         "flash_self=run ramargs addip addtty addmtd addmisc;"           \
 320                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 321         "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
 322                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 323         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 324                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 325                 "run nfsargs addip addtty addmtd addmisc;"              \
 326                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 327         "bootcmd=run flash_self\0"                                      \
 328         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 329         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 330                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 331                 " +${filesize};cp.b ${fileaddr} "                       \
 332                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 333         "upd=run load update\0"                                         \
 334
 335 #endif  /* __CONFIG_H */