include/configs/mpc8308_p1m.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15
  16 /*
  17  * On-board devices
  18  *
  19  * TSECs
  20  */
  21 #define CONFIG_TSEC1
  22 #define CONFIG_TSEC2
  23
  24 /*
  25  * System IO Config
  26  */
  27 #define CONFIG_SYS_SICRH (\
  28         SICRH_ESDHC_A_GPIO |\
  29         SICRH_ESDHC_B_GPIO |\
  30         SICRH_ESDHC_C_GTM |\
  31         SICRH_GPIO_A_TSEC2 |\
  32         SICRH_GPIO_B_TSEC2_TX_CLK |\
  33         SICRH_IEEE1588_A_GPIO |\
  34         SICRH_USB |\
  35         SICRH_GTM_GPIO |\
  36         SICRH_IEEE1588_B_GPIO |\
  37         SICRH_ETSEC2_CRS |\
  38         SICRH_GPIOSEL_1 |\
  39         SICRH_TMROBI_V3P3 |\
  40         SICRH_TSOBI1_V3P3 |\
  41         SICRH_TSOBI2_V3P3)      /* 0xf577d100 */
  42 #define CONFIG_SYS_SICRL (\
  43         SICRL_SPI_PF0 |\
  44         SICRL_UART_PF0 |\
  45         SICRL_IRQ_PF0 |\
  46         SICRL_I2C2_PF0 |\
  47         SICRL_ETSEC1_TX_CLK)    /* 0x00000000 */
  48
  49 #define CONFIG_SYS_GPIO1_PRELIM
  50 /* GPIO Default input/output settings */
  51 #define CONFIG_SYS_GPIO1_DIR        0x7AAF8C00
  52 /*
  53  * Default GPIO values:
  54  * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
  55  */
  56 #define CONFIG_SYS_GPIO1_DAT        0x08008C00
  57
  58 /*
  59  * IMMR new address
  60  */
  61 #define CONFIG_SYS_IMMR         0xE0000000
  62
  63 /*
  64  * SERDES
  65  */
  66 #define CONFIG_FSL_SERDES
  67 #define CONFIG_FSL_SERDES1      0xe3000
  68
  69 /*
  70  * Arbiter Setup
  71  */
  72 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  73 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  74 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
  75
  76 /*
  77  * DDR Setup
  78  */
  79 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  80 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  81 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  82 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  83 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  84                                 | DDRCDR_PZ_LOZ \
  85                                 | DDRCDR_NZ_LOZ \
  86                                 | DDRCDR_ODT \
  87                                 | DDRCDR_Q_DRN)
  88                                 /* 0x7b880001 */
  89 /*
  90  * Manually set up DDR parameters
  91  * consist of two chips HY5PS12621BFP-C4 from HYNIX
  92  */
  93
  94 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
  95
  96 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  97 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  98                                         | CSCONFIG_ODT_RD_NEVER \
  99                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
 100                                         | CSCONFIG_ROW_BIT_13 \
 101                                         | CSCONFIG_COL_BIT_10)
 102                                         /* 0x80010102 */
 103 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 104 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 105                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 106                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 107                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 108                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 109                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 110                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 111                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 112                                 /* 0x00220802 */
 113 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 114                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 115                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 116                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 117                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
 118                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 119                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 120                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 121                                 /* 0x27256222 */
 122 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 123                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 124                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 125                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 126                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 127                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 128                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 129                                 /* 0x121048c5 */
 130 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 131                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 132                                 /* 0x03600100 */
 133 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 134                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 135                                 | SDRAM_CFG_DBW_32)
 136                                 /* 0x43080000 */
 137
 138 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 139 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 140                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 141                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 142 #define CONFIG_SYS_DDR_MODE2            0x00000000
 143
 144 /*
 145  * Memory test
 146  */
 147 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 148 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 149
 150 /*
 151  * The reserved memory
 152  */
 153 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 154
 155 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 156 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 157
 158 /*
 159  * Initial RAM Base Address Setup
 160  */
 161 #define CONFIG_SYS_INIT_RAM_LOCK        1
 162 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 163 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 164 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 165         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 166
 167 /*
 168  * Local Bus Configuration & Clock Setup
 169  */
 170 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 171 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 172 #define CONFIG_SYS_LBC_LBCR             0x00040000
 173
 174 /*
 175  * FLASH on the Local Bus
 176  */
 177 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 178
 179 #define CONFIG_SYS_FLASH_BASE           0xFC000000 /* FLASH base address */
 180 #define CONFIG_SYS_FLASH_SIZE           64 /* FLASH size is 64M */
 181
 182 /* Window base at flash base */
 183 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 184 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 185
 186 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 187                                 | BR_PS_16      /* 16 bit port */ \
 188                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 189                                 | BR_V)         /* valid */
 190 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 191                                 | OR_UPM_XAM \
 192                                 | OR_GPCM_CSNT \
 193                                 | OR_GPCM_ACS_DIV2 \
 194                                 | OR_GPCM_XACS \
 195                                 | OR_GPCM_SCY_4 \
 196                                 | OR_GPCM_TRLX_SET \
 197                                 | OR_GPCM_EHTR_SET)
 198
 199 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 200 #define CONFIG_SYS_MAX_FLASH_SECT       512
 201
 202 /* Flash Erase Timeout (ms) */
 203 #define CONFIG_SYS_FLASH_ERASE_TOUT     (1000 * 1024)
 204 /* Flash Write Timeout (ms) */
 205 #define CONFIG_SYS_FLASH_WRITE_TOUT     (500 * 1024)
 206
 207 /*
 208  * SJA1000 CAN controller on Local Bus
 209  */
 210 #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
 211 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_SJA1000_BASE \
 212                                 | BR_PS_8       /* 8 bit port size */ \
 213                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 214                                 | BR_V)         /* valid */
 215 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
 216                                 | OR_GPCM_SCY_5 \
 217                                 | OR_GPCM_EHTR_SET)
 218                                 /* 0xFFFF8052 */
 219
 220 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_SJA1000_BASE
 221 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 222
 223 /*
 224  * CPLD on Local Bus
 225  */
 226 #define CONFIG_SYS_CPLD_BASE    0xFBFF8000
 227 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_CPLD_BASE \
 228                                 | BR_PS_8       /* 8 bit port */ \
 229                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 230                                 | BR_V)         /* valid */
 231 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_32KB \
 232                                 | OR_GPCM_SCY_4 \
 233                                 | OR_GPCM_EHTR_SET)
 234                                 /* 0xFFFF8042 */
 235
 236 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_CPLD_BASE
 237 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 238
 239 /*
 240  * Serial Port
 241  */
 242 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 243 #define CONFIG_SYS_NS16550_SERIAL
 244 #define CONFIG_SYS_NS16550_REG_SIZE     1
 245 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 246
 247 #define CONFIG_SYS_BAUDRATE_TABLE  \
 248         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 249
 250 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 251 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 252
 253 /* I2C */
 254 #define CONFIG_SYS_I2C
 255 #define CONFIG_SYS_I2C_FSL
 256 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 257 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 258 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 259 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 260 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 261 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 262
 263 /*
 264  * General PCI
 265  * Addresses are mapped 1-1.
 266  */
 267 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 268 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 269 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 270 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 271 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 272 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 273 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 274 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 275 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 276
 277 /* enable PCIE clock */
 278 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 279
 280 #define CONFIG_PCI_INDIRECT_BRIDGE
 281 #define CONFIG_PCIE
 282
 283 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 284 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 285
 286 /*
 287  * TSEC
 288  */
 289 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 290 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 291 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 292 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 293
 294 /*
 295  * TSEC ethernet configuration
 296  */
 297 #define CONFIG_TSEC1_NAME       "eTSEC0"
 298 #define CONFIG_TSEC2_NAME       "eTSEC1"
 299 #define TSEC1_PHY_ADDR          1
 300 #define TSEC2_PHY_ADDR          2
 301 #define TSEC1_PHYIDX            0
 302 #define TSEC2_PHYIDX            0
 303 #define TSEC1_FLAGS             0
 304 #define TSEC2_FLAGS             0
 305
 306 /* Options are: eTSEC[0-1] */
 307 #define CONFIG_ETHPRIME         "eTSEC0"
 308
 309 /*
 310  * Environment
 311  */
 312 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 313                                  CONFIG_SYS_MONITOR_LEN)
 314 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 315 #define CONFIG_ENV_SIZE         0x2000
 316 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 317 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 318
 319 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 320 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 321
 322 /*
 323  * BOOTP options
 324  */
 325 #define CONFIG_BOOTP_BOOTFILESIZE
 326
 327 /*
 328  * Command line configuration.
 329  */
 330
 331 /*
 332  * Miscellaneous configurable options
 333  */
 334 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 335
 336 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 337
 338 /* Boot Argument Buffer Size */
 339 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 340
 341 /*
 342  * For booting Linux, the board info and command line data
 343  * have to be in the first 8 MB of memory, since this is
 344  * the maximum mapped by the Linux kernel during initialization.
 345  */
 346 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 347
 348 /*
 349  * Core HID Setup
 350  */
 351 #define CONFIG_SYS_HID0_INIT    0x000000000
 352 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 353                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 354                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 355 #define CONFIG_SYS_HID2         HID2_HBE
 356
 357 /*
 358  * Environment Configuration
 359  */
 360
 361 #define CONFIG_ENV_OVERWRITE
 362
 363 #if defined(CONFIG_TSEC_ENET)
 364 #define CONFIG_HAS_ETH0
 365 #define CONFIG_HAS_ETH1
 366 #endif
 367
 368 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 369
 370
 371 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 372         "netdev=eth0\0"                                                 \
 373         "consoledev=ttyS0\0"                                            \
 374         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 375                 "nfsroot=${serverip}:${rootpath}\0"                     \
 376         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 377         "addip=setenv bootargs ${bootargs} "                            \
 378                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 379                 ":${hostname}:${netdev}:off panic=1\0"                  \
 380         "addtty=setenv bootargs ${bootargs}"                            \
 381                 " console=${consoledev},${baudrate}\0"                  \
 382         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 383         "addmisc=setenv bootargs ${bootargs}\0"                         \
 384         "kernel_addr=FC0A0000\0"                                        \
 385         "fdt_addr=FC2A0000\0"                                           \
 386         "ramdisk_addr=FC2C0000\0"                                       \
 387         "u-boot=mpc8308_p1m/u-boot.bin\0"                               \
 388         "kernel_addr_r=1000000\0"                                       \
 389         "fdt_addr_r=C00000\0"                                           \
 390         "hostname=mpc8308_p1m\0"                                        \
 391         "bootfile=mpc8308_p1m/uImage\0"                                 \
 392         "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0"                         \
 393         "rootpath=/opt/eldk-4.2/ppc_6xx\0"                              \
 394         "flash_self=run ramargs addip addtty addmtd addmisc;"           \
 395                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 396         "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
 397                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 398         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 399                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 400                 "run nfsargs addip addtty addmtd addmisc;"              \
 401                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 402         "bootcmd=run flash_self\0"                                      \
 403         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 404         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 405                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 406                 " +${filesize};cp.b ${fileaddr} "                       \
 407                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 408         "upd=run load update\0"                                         \
 409
 410 #endif  /* __CONFIG_H */