include/configs/mpc5121ads.h

   1 /*
   2  * (C) Copyright 2007-2009 DENX Software Engineering
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * MPC5121ADS board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #define CONFIG_MPC5121ADS 1
  15
  16 /*
  17  * Memory map for the MPC5121ADS board:
  18  *
  19  * 0x0000_0000 - 0x0FFF_FFFF    DDR RAM (256 MB)
  20  * 0x3000_0000 - 0x3001_FFFF    SRAM (128 KB)
  21  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
  22  * 0x8200_0000 - 0x8200_001F    CPLD (32 B)
  23  * 0x8400_0000 - 0x82FF_FFFF    PCI I/O space (16 MB)
  24  * 0xA000_0000 - 0xAFFF_FFFF    PCI memory space (256 MB)
  25  * 0xB000_0000 - 0xBFFF_FFFF    PCI memory mapped I/O space (256 MB)
  26  * 0xFC00_0000 - 0xFFFF_FFFF    NOR Boot FLASH (64 MB)
  27  */
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_E300             1       /* E300 Family */
  33
  34 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  35
  36 /* video */
  37 #ifdef CONFIG_FSL_DIU_FB
  38 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_IMMR + 0x2100)
  39 #define CONFIG_CMD_BMP
  40 #define CONFIG_VIDEO_LOGO
  41 #define CONFIG_VIDEO_BMP_LOGO
  42 #endif
  43
  44 /* CONFIG_PCI is defined at config time */
  45
  46 #ifdef CONFIG_MPC5121ADS_REV2
  47 #define CONFIG_SYS_MPC512X_CLKIN        66000000        /* in Hz */
  48 #else
  49 #define CONFIG_SYS_MPC512X_CLKIN        33333333        /* in Hz */
  50 #endif
  51
  52 #define CONFIG_MISC_INIT_R
  53
  54 #define CONFIG_SYS_IMMR         0x80000000
  55
  56 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  57 #define CONFIG_SYS_MEMTEST_END          0x00400000
  58
  59 /*
  60  * DDR Setup - manually set all parameters as there's no SPD etc.
  61  */
  62 #ifdef CONFIG_MPC5121ADS_REV2
  63 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  64 #else
  65 #define CONFIG_SYS_DDR_SIZE             512             /* MB */
  66 #endif
  67 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
  68 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  69 #define CONFIG_SYS_MAX_RAM_SIZE         0x20000000
  70
  71 #define CONFIG_SYS_IOCTRL_MUX_DDR       0x00000036
  72
  73 /* DDR Controller Configuration
  74  *
  75  * SYS_CFG:
  76  *      [31:31] MDDRC Soft Reset:       Diabled
  77  *      [30:30] DRAM CKE pin:           Enabled
  78  *      [29:29] DRAM CLK:               Enabled
  79  *      [28:28] Command Mode:           Enabled (For initialization only)
  80  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
  81  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
  82  *      [20:19] Read Test:              DON'T USE
  83  *      [18:18] Self Refresh:           Enabled
  84  *      [17:17] 16bit Mode:             Disabled
  85  *      [16:13] Ready Delay:            2
  86  *      [12:12] Half DQS Delay:         Disabled
  87  *      [11:11] Quarter DQS Delay:      Disabled
  88  *      [10:08] Write Delay:            2
  89  *      [07:07] Early ODT:              Disabled
  90  *      [06:06] On DIE Termination:     Disabled
  91  *      [05:05] FIFO Overflow Clear:    DON'T USE here
  92  *      [04:04] FIFO Underflow Clear:   DON'T USE here
  93  *      [03:03] FIFO Overflow Pending:  DON'T USE here
  94  *      [02:02] FIFO Underlfow Pending: DON'T USE here
  95  *      [01:01] FIFO Overlfow Enabled:  Enabled
  96  *      [00:00] FIFO Underflow Enabled: Enabled
  97  * TIME_CFG0
  98  *      [31:16] DRAM Refresh Time:      0 CSB clocks
  99  *      [15:8]  DRAM Command Time:      0 CSB clocks
 100  *      [07:00] DRAM Precharge Time:    0 CSB clocks
 101  * TIME_CFG1
 102  *      [31:26] DRAM tRFC:
 103  *      [25:21] DRAM tWR1:
 104  *      [20:17] DRAM tWRT1:
 105  *      [16:11] DRAM tDRR:
 106  *      [10:05] DRAM tRC:
 107  *      [04:00] DRAM tRAS:
 108  * TIME_CFG2
 109  *      [31:28] DRAM tRCD:
 110  *      [27:23] DRAM tFAW:
 111  *      [22:19] DRAM tRTW1:
 112  *      [18:15] DRAM tCCD:
 113  *      [14:10] DRAM tRTP:
 114  *      [09:05] DRAM tRP:
 115  *      [04:00] DRAM tRPA
 116  */
 117 #ifdef CONFIG_MPC5121ADS_REV2
 118 #define CONFIG_SYS_MDDRC_SYS_CFG        0xE8604A00
 119 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x54EC1168
 120 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x35210864
 121 #else
 122 #define CONFIG_SYS_MDDRC_SYS_CFG        0xEA804A00
 123 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x68EC1168
 124 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x34310864
 125 #endif
 126 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x06183D2E
 127
 128 #define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA         0xEA802B00
 129 #define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA       0x690e1189
 130 #define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA       0x35310864
 131
 132 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
 133 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
 134 #define CONFIG_SYS_DDRCMD_EM2           0x01020000
 135 #define CONFIG_SYS_DDRCMD_EM3           0x01030000
 136 #define CONFIG_SYS_DDRCMD_EN_DLL        0x01010000
 137 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
 138
 139 #define DDRCMD_EMR_OCD(pr, ohm) ( \
 140         (1 << 24)          | /* MDDRC Command Request   */ \
 141         (1 << 16)          | /* MODE Reg BA[2:0]        */ \
 142         (0 << 12)          | /* Outputs 0=Enabled       */ \
 143         (0 << 11)          | /* RDQS                    */ \
 144         (1 << 10)          | /* DQS#                    */ \
 145         (pr <<  7)         | /* OCD prog 7=deflt,0=exit */ \
 146                     /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
 147         ((ohm & 0x2) <<  5)| /* Rtt1                    */ \
 148         (0 <<  3)          | /* additive posted CAS#    */ \
 149         ((ohm & 0x1) <<  2)| /* Rtt0                    */ \
 150         (0 <<  0)          | /* Output Drive Strength   */ \
 151         (0 <<  0))           /* DLL Enable 0=Normal     */
 152
 153 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   DDRCMD_EMR_OCD(7, 0)
 154 #define CONFIG_SYS_ELPIDA_OCD_EXIT      DDRCMD_EMR_OCD(0, 0)
 155
 156 #define DDRCMD_MODE_REG(cas, wr) ( \
 157         (1 << 24)    | /* MDDRC Command Request                 */ \
 158         (0 << 16)    | /* MODE Reg BA[2:0]                      */ \
 159         ((wr-1) << 9)| /* Write Recovery                        */ \
 160         (cas << 4)   | /* CAS                                   */ \
 161         (0 << 3)     | /* Burst Type:0=Sequential,1=Interleaved */ \
 162         (2 << 0))      /* 4 or 8 Burst Length:0x2=4 0x3=8       */
 163
 164 #define CONFIG_SYS_MICRON_INIT_DEV_OP   DDRCMD_MODE_REG(3, 3)
 165 #define CONFIG_SYS_ELPIDA_INIT_DEV_OP   DDRCMD_MODE_REG(4, 4)
 166 #define CONFIG_SYS_ELPIDA_RES_DLL       (DDRCMD_MODE_REG(4, 4) | (1 << 8))
 167
 168 /* DDR Priority Manager Configuration */
 169 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
 170 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
 171 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
 172 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
 173 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
 174 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
 175 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
 176 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
 177 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
 178 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
 179 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
 180 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
 181 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
 182 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
 183 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
 184 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
 185 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
 186 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
 187 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
 188 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
 189 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
 190 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
 191 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
 192
 193 /*
 194  * NOR FLASH on the Local Bus
 195  */
 196 #undef CONFIG_BKUP_FLASH
 197 #define CONFIG_SYS_FLASH_CFI                            /* use the Common Flash Interface */
 198 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
 199 #ifdef CONFIG_BKUP_FLASH
 200 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
 201 #define CONFIG_SYS_FLASH_SIZE           0x00800000      /* max flash size in bytes */
 202 #else
 203 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* start of FLASH   */
 204 #define CONFIG_SYS_FLASH_SIZE           0x04000000      /* max flash size in bytes */
 205 #endif
 206 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 207 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 208 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 209 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max sectors per device */
 210
 211 #undef CONFIG_SYS_FLASH_CHECKSUM
 212
 213 /*
 214  * NAND FLASH
 215  * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
 216  */
 217 #define CONFIG_CMD_NAND                                 /* enable NAND support */
 218 #define CONFIG_JFFS2_NAND                               /* with JFFS2 on it */
 219 #define CONFIG_NAND_MPC5121_NFC
 220 #define CONFIG_SYS_NAND_BASE            0x40000000
 221
 222 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 223 #define CONFIG_SYS_NAND_SELECT_DEVICE   /* driver supports mutipl. chips */
 224
 225 /*
 226  * Configuration parameters for MPC5121 NAND driver
 227  */
 228 #define CONFIG_FSL_NFC_WIDTH 1
 229 #define CONFIG_FSL_NFC_WRITE_SIZE 2048
 230 #define CONFIG_FSL_NFC_SPARE_SIZE 64
 231 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
 232
 233 /*
 234  * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
 235  * window is 64KB
 236  */
 237 #define CONFIG_SYS_CPLD_BASE            0x82000000
 238 #define CONFIG_SYS_CPLD_SIZE            0x00010000      /* 64 KB */
 239 #define CONFIG_SYS_CS2_START            CONFIG_SYS_CPLD_BASE
 240 #define CONFIG_SYS_CS2_SIZE             CONFIG_SYS_CPLD_SIZE
 241
 242 #define CONFIG_SYS_SRAM_BASE            0x30000000
 243 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
 244
 245 #define CONFIG_SYS_CS0_CFG              0x05059310      /* ALE active low, data size 4bytes */
 246 #define CONFIG_SYS_CS2_CFG              0x05059010      /* ALE active low, data size 1byte */
 247 #define CONFIG_SYS_CS_ALETIMING 0x00000005      /* Use alternative CS timing for CS0 and CS2 */
 248
 249 /* Use SRAM for initial stack */
 250 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_SRAM_BASE            /* Initial RAM address */
 251 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_SRAM_SIZE            /* Size of used area in RAM */
 252
 253 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 254 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 255
 256 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE            /* Start of monitor */
 257 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)            /* Reserve 512 kB for Mon */
 258 #ifdef  CONFIG_FSL_DIU_FB
 259 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)       /* Reserved for malloc */
 260 #else
 261 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 262 #endif
 263
 264 /*
 265  * Serial Port
 266  */
 267 #define CONFIG_CONS_INDEX     1
 268
 269 /*
 270  * Serial console configuration
 271  */
 272 #define CONFIG_PSC_CONSOLE      3       /* console is on PSC3 */
 273 #define CONFIG_SYS_PSC3
 274 #if CONFIG_PSC_CONSOLE != 3
 275 #error CONFIG_PSC_CONSOLE must be 3
 276 #endif
 277 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
 278 #define CONFIG_SYS_BAUDRATE_TABLE  \
 279         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 280
 281 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC3_TX_SIZE
 282 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC3_TX_ADDR
 283 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC3_RX_SIZE
 284 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC3_RX_ADDR
 285
 286 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 287
 288 /*
 289  * Clocks in use
 290  */
 291 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
 292                          CLOCK_SCCR1_DDR_EN |                           \
 293                          CLOCK_SCCR1_FEC_EN |                           \
 294                          CLOCK_SCCR1_LPC_EN |                           \
 295                          CLOCK_SCCR1_NFC_EN |                           \
 296                          CLOCK_SCCR1_PATA_EN |                          \
 297                          CLOCK_SCCR1_PCI_EN |                           \
 298                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
 299                          CLOCK_SCCR1_PSCFIFO_EN |                       \
 300                          CLOCK_SCCR1_TPR_EN)
 301
 302 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN |           \
 303                          CLOCK_SCCR2_I2C_EN |           \
 304                          CLOCK_SCCR2_MEM_EN |           \
 305                          CLOCK_SCCR2_SPDIF_EN |         \
 306                          CLOCK_SCCR2_USB1_EN |          \
 307                          CLOCK_SCCR2_USB2_EN)
 308
 309 /*
 310  * PCI
 311  */
 312 #ifdef CONFIG_PCI
 313 #define CONFIG_PCI_INDIRECT_BRIDGE
 314
 315 /*
 316  * General PCI
 317  */
 318 #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
 319 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
 320 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000      /* 256M */
 321 #define CONFIG_SYS_PCI_MMIO_BASE        (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
 322 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 323 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000      /* 256M */
 324 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 325 #define CONFIG_SYS_PCI_IO_PHYS          0x84000000
 326 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000      /* 16M */
 327
 328 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 329
 330 #endif
 331
 332 /* I2C */
 333 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 334 #define CONFIG_I2C_MULTI_BUS
 335 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address */
 336 #define CONFIG_SYS_I2C_SLAVE            0x7F
 337 #if 0
 338 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}      /* Don't probe these addrs */
 339 #endif
 340
 341 /*
 342  * IIM - IC Identification Module
 343  */
 344 #undef CONFIG_FSL_IIM
 345
 346 /*
 347  * EEPROM configuration
 348  */
 349 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16-bit EEPROM address */
 350 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* Atmel: AT24C32A-10TQ-2.7 */
 351 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* 10ms of delay */
 352 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 32-Byte Page Write Mode */
 353
 354 /*
 355  * Ethernet configuration
 356  */
 357 #define CONFIG_MPC512x_FEC      1
 358 #define CONFIG_PHY_ADDR         0x1
 359 #define CONFIG_MII              1       /* MII PHY management           */
 360 #define CONFIG_FEC_AN_TIMEOUT   1
 361 #define CONFIG_HAS_ETH0
 362
 363 /*
 364  * Configure on-board RTC
 365  */
 366 #define CONFIG_RTC_M41T62                       /* use M41T62 rtc via i2 */
 367 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68              */
 368
 369 /*
 370  * USB  Support
 371  */
 372
 373 #if defined(CONFIG_CMD_USB)
 374 #define CONFIG_USB_EHCI                         /* Enable EHCI Support  */
 375 #define CONFIG_USB_EHCI_FSL                     /* On a FSL platform    */
 376 #define CONFIG_EHCI_MMIO_BIG_ENDIAN             /* With big-endian regs */
 377 #define CONFIG_EHCI_DESC_BIG_ENDIAN
 378 #define CONFIG_EHCI_IS_TDI
 379 #endif
 380
 381 /*
 382  * Environment
 383  */
 384 #define CONFIG_ENV_IS_IN_FLASH  1
 385 /* This has to be a multiple of the Flash sector size */
 386 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 387 #define CONFIG_ENV_SIZE         0x2000
 388 #ifdef CONFIG_BKUP_FLASH
 389 #define CONFIG_ENV_SECT_SIZE    0x20000 /* one sector (256K) for env */
 390 #else
 391 #define CONFIG_ENV_SECT_SIZE    0x40000 /* one sector (256K) for env */
 392 #endif
 393
 394 /* Address and size of Redundant Environment Sector     */
 395 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 396 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 397
 398 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 399 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 400
 401 #define CONFIG_CMD_DATE
 402 #define CONFIG_CMD_EEPROM
 403 #define CONFIG_CMD_IDE
 404 #define CONFIG_CMD_JFFS2
 405 #define CONFIG_CMD_REGINFO
 406
 407 #undef CONFIG_CMD_FUSE
 408
 409 #if defined(CONFIG_PCI)
 410 #define CONFIG_CMD_PCI
 411 #endif
 412
 413 /*
 414  * Dynamic MTD partition support
 415  */
 416 #define CONFIG_CMD_MTDPARTS
 417 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 418 #define CONFIG_FLASH_CFI_MTD
 419 #define MTDIDS_DEFAULT          "nor0=fc000000.flash,nand0=mpc5121.nand"
 420
 421 /*
 422  * NOR flash layout:
 423  *
 424  * FC000000 - FEABFFFF 42.75 MiB        User Data
 425  * FEAC0000 - FFABFFFF  16 MiB          Root File System
 426  * FFAC0000 - FFEBFFFF   4 MiB          Linux Kernel
 427  * FFEC0000 - FFEFFFFF 256 KiB          Device Tree
 428  * FFF00000 - FFFFFFFF   1 MiB          U-Boot (up to 512 KiB) and 2 x * env
 429  *
 430  * NAND flash layout: one big partition
 431  */
 432 #define MTDPARTS_DEFAULT        "mtdparts=fc000000.flash:43776k(user)," \
 433                                                 "16m(rootfs),"          \
 434                                                 "4m(kernel),"           \
 435                                                 "256k(dtb),"            \
 436                                                 "1m(u-boot);"           \
 437                                         "mpc5121.nand:-(data)"
 438
 439 #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
 440 #define CONFIG_SUPPORT_VFAT
 441
 442 #endif /* defined(CONFIG_CMD_IDE) */
 443
 444 /*
 445  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
 446  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
 447  * to 0xFFFF, watchdog timeouts after about 64s. For details refer
 448  * to chapter 36 of the MPC5121e Reference Manual.
 449  */
 450 /* #define CONFIG_WATCHDOG */           /* enable watchdog */
 451 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
 452
 453  /*
 454  * Miscellaneous configurable options
 455  */
 456 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 457 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 458
 459 #ifdef CONFIG_CMD_KGDB
 460         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 461 #else
 462         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 463 #endif
 464
 465 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 466 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 467 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 468
 469 /*
 470  * For booting Linux, the board info and command line data
 471  * have to be in the first 256 MB of memory, since this is
 472  * the maximum mapped by the Linux kernel during initialization.
 473  */
 474 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 475
 476 /* Cache Configuration */
 477 #define CONFIG_SYS_DCACHE_SIZE          32768
 478 #define CONFIG_SYS_CACHELINE_SIZE       32
 479 #ifdef CONFIG_CMD_KGDB
 480 #define CONFIG_SYS_CACHELINE_SHIFT      5       /*log base 2 of the above value*/
 481 #endif
 482
 483 #define CONFIG_SYS_HID0_INIT    0x000000000
 484 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
 485 #define CONFIG_SYS_HID2 HID2_HBE
 486
 487 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 488
 489 #ifdef CONFIG_CMD_KGDB
 490 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 491 #endif
 492
 493 /*
 494  * Environment Configuration
 495  */
 496 #define CONFIG_TIMESTAMP
 497
 498 #define CONFIG_HOSTNAME         mpc5121ads
 499 #define CONFIG_BOOTFILE         "mpc5121ads/uImage"
 500 #define CONFIG_ROOTPATH         "/opt/eldk/ppc_6xx"
 501
 502 #define CONFIG_LOADADDR         400000  /* default location for tftp and bootm */
 503
 504 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 505
 506 #define CONFIG_BAUDRATE         115200
 507
 508 #define CONFIG_PREBOOT  "echo;" \
 509         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 510         "echo"
 511
 512 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 513         "u-boot_addr_r=200000\0"                                        \
 514         "kernel_addr_r=600000\0"                                        \
 515         "fdt_addr_r=880000\0"                                           \
 516         "ramdisk_addr_r=900000\0"                                       \
 517         "u-boot_addr=FFF00000\0"                                        \
 518         "kernel_addr=FFAC0000\0"                                        \
 519         "fdt_addr=FFEC0000\0"                                           \
 520         "ramdisk_addr=FEAC0000\0"                                       \
 521         "ramdiskfile=mpc5121ads/uRamdisk\0"                             \
 522         "u-boot=mpc5121ads/u-boot.bin\0"                                \
 523         "bootfile=mpc5121ads/uImage\0"                                  \
 524         "fdtfile=mpc5121ads/mpc5121ads.dtb\0"                           \
 525         "rootpath=/opt/eldk/ppc_6xx\n"                                  \
 526         "netdev=eth0\0"                                                 \
 527         "consdev=ttyPSC0\0"                                             \
 528         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 529                 "nfsroot=${serverip}:${rootpath}\0"                     \
 530         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 531         "addip=setenv bootargs ${bootargs} "                            \
 532                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 533                 ":${hostname}:${netdev}:off panic=1\0"                  \
 534         "addtty=setenv bootargs ${bootargs} "                           \
 535                 "console=${consdev},${baudrate}\0"                      \
 536         "flash_nfs=run nfsargs addip addtty;"                           \
 537                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 538         "flash_self=run ramargs addip addtty;"                          \
 539                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 540         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 541                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 542                 "run nfsargs addip addtty;"                             \
 543                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 544         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
 545                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
 546                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 547                 "run ramargs addip addtty;"                             \
 548                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
 549         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 550         "update=protect off ${u-boot_addr} +${filesize};"               \
 551                 "era ${u-boot_addr} +${filesize};"                      \
 552                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
 553         "upd=run load update\0"                                         \
 554         ""
 555
 556 #define CONFIG_BOOTCOMMAND      "run flash_self"
 557
 558 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
 559
 560 #define OF_CPU                  "PowerPC,5121@0"
 561 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
 562 #define OF_TBCLK                (bd->bi_busfreq / 4)
 563 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
 564
 565 /*-----------------------------------------------------------------------
 566  * IDE/ATA stuff
 567  *-----------------------------------------------------------------------
 568  */
 569
 570 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 571 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 572 #undef  CONFIG_IDE_LED                  /* LED   for IDE not supported  */
 573
 574 #define CONFIG_IDE_RESET                /* reset for IDE supported      */
 575 #define CONFIG_IDE_PREINIT
 576
 577 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 578 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
 579
 580 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 581 #define CONFIG_SYS_ATA_BASE_ADDR        get_pata_base()
 582
 583 /* Offset for data I/O                  RefMan MPC5121EE Table 28-10    */
 584 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x00A0)
 585
 586 /* Offset for normal register accesses  */
 587 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 588
 589 /* Offset for alternate registers       RefMan MPC5121EE Table 28-23    */
 590 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x00D8)
 591
 592 /* Interval between registers   */
 593 #define CONFIG_SYS_ATA_STRIDE           4
 594
 595 #define ATA_BASE_ADDR                   get_pata_base()
 596
 597 /*
 598  * Control register bit definitions
 599  */
 600 #define FSL_ATA_CTRL_FIFO_RST_B         0x80000000
 601 #define FSL_ATA_CTRL_ATA_RST_B          0x40000000
 602 #define FSL_ATA_CTRL_FIFO_TX_EN         0x20000000
 603 #define FSL_ATA_CTRL_FIFO_RCV_EN        0x10000000
 604 #define FSL_ATA_CTRL_DMA_PENDING        0x08000000
 605 #define FSL_ATA_CTRL_DMA_ULTRA          0x04000000
 606 #define FSL_ATA_CTRL_DMA_WRITE          0x02000000
 607 #define FSL_ATA_CTRL_IORDY_EN           0x01000000
 608
 609 #endif  /* __CONFIG_H */