2 * Copyright (C) 2014 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_SYS_GENERIC_BOARD
12 #define CONFIG_REMAKE_ELF
13 #define CONFIG_FSL_LSCH3
14 #define CONFIG_LS2085A
16 #define CONFIG_FSL_TZPC_BP147
19 #define CONFIG_ARM_ERRATA_828024
20 #define CONFIG_ARM_ERRATA_826974
22 /* We need architecture specific misc initializations */
23 #define CONFIG_ARCH_MISC_INIT
25 /* Link Definitions */
26 #define CONFIG_SYS_TEXT_BASE 0x30001000
29 #define CONFIG_SYS_NO_FLASH
32 #define CONFIG_SUPPORT_RAW_INITRD
34 #define CONFIG_SKIP_LOWLEVEL_INIT
35 #define CONFIG_BOARD_EARLY_INIT_F 1
37 /* Flat Device Tree Definitions */
38 #define CONFIG_OF_LIBFDT
39 #define CONFIG_OF_BOARD_SETUP
41 /* new uImage format support */
43 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
45 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
46 #ifndef CONFIG_SYS_FSL_DDR4
47 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
48 #define CONFIG_SYS_DDR_RAW_TIMING
50 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
51 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
53 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
55 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
56 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
57 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
58 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
59 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
64 #define CPU_RELEASE_ADDR secondary_boot_func
66 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
67 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
69 * DDR controller use 0 as the base address for binding.
70 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
72 #define CONFIG_SYS_DP_DDR_BASE_PHY 0
73 #define CONFIG_DP_DDR_CTRL 2
74 #define CONFIG_DP_DDR_NUM_CTRLS 1
75 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
77 /* Generic Timer Definitions */
78 #define COUNTER_FREQUENCY 12000000 /* 12MHz */
80 /* Size of malloc() pool */
81 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
84 #define CONFIG_CMD_I2C
85 #define CONFIG_SYS_I2C
86 #define CONFIG_SYS_I2C_MXC
87 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
88 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
89 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000
90 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000
93 #define CONFIG_CONS_INDEX 2
94 #define CONFIG_SYS_NS16550
95 #define CONFIG_SYS_NS16550_SERIAL
96 #define CONFIG_SYS_NS16550_REG_SIZE 1
97 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
99 #define CONFIG_BAUDRATE 115200
100 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
103 #define CONFIG_FSL_IFC
104 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
105 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
107 * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
108 * address 0. But this region is limited to 256MB. To accommodate bigger NOR
109 * flash and other devices, we will map CS0 to 0x580000000 after relocation.
110 * CONFIG_SYS_FLASH_BASE has the final address (core view)
111 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
112 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
113 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
115 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
116 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
117 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
120 * NOR Flash Timing Params
122 #define CONFIG_SYS_NOR0_CSPR \
123 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
124 CSPR_PORT_SIZE_16 | \
127 #define CONFIG_SYS_NOR0_CSPR_EARLY \
128 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
129 CSPR_PORT_SIZE_16 | \
132 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
133 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
134 FTIM0_NOR_TEADC(0x1) | \
135 FTIM0_NOR_TEAHC(0x1))
136 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
137 FTIM1_NOR_TRAD_NOR(0x1))
138 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
139 FTIM2_NOR_TCH(0x0) | \
141 #define CONFIG_SYS_NOR_FTIM3 0x04000000
142 #define CONFIG_SYS_IFC_CCR 0x01000000
144 #ifndef CONFIG_SYS_NO_FLASH
145 #define CONFIG_FLASH_CFI_DRIVER
146 #define CONFIG_SYS_FLASH_CFI
147 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
148 #define CONFIG_SYS_FLASH_QUIET_TEST
149 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
151 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
152 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
153 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
154 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
156 #define CONFIG_SYS_FLASH_EMPTY_INFO
157 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
160 #define CONFIG_NAND_FSL_IFC
161 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
162 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
163 #define CONFIG_SYS_NAND_BASE 0x520000000
164 #define CONFIG_SYS_NAND_BASE_PHYS 0x20000000
166 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
167 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
168 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
169 | CSPR_MSEL_NAND /* MSEL = NAND */ \
171 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
173 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
174 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
175 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
176 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
177 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
178 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
179 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
181 #define CONFIG_SYS_NAND_ONFI_DETECTION
183 /* ONFI NAND Flash mode0 Timing Params */
184 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
185 FTIM0_NAND_TWP(0x18) | \
186 FTIM0_NAND_TWCHT(0x07) | \
187 FTIM0_NAND_TWH(0x0a))
188 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
189 FTIM1_NAND_TWBE(0x39) | \
190 FTIM1_NAND_TRR(0x0e) | \
191 FTIM1_NAND_TRP(0x18))
192 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
193 FTIM2_NAND_TREH(0x0a) | \
194 FTIM2_NAND_TWHRE(0x1e))
195 #define CONFIG_SYS_NAND_FTIM3 0x0
197 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
198 #define CONFIG_SYS_MAX_NAND_DEVICE 1
199 #define CONFIG_CMD_NAND
201 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
203 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
204 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
205 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
206 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
207 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
208 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
209 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
210 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
211 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
213 /* Debug Server firmware */
214 #define CONFIG_FSL_DEBUG_SERVER
215 #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
216 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
217 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
219 #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
222 #define CONFIG_FSL_MC_ENET
223 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
224 #define CONFIG_SYS_LS_MC_FW_IN_NOR
225 #define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL
226 #define CONFIG_SYS_LS_MC_DPL_IN_NOR
227 #define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
228 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
229 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH (256 * 1024)
230 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000
232 /* Carve out a DDR region which will not be used by u-boot/Linux */
233 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
234 #define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide()
237 /* Command line configuration */
238 #define CONFIG_CMD_CACHE
239 #define CONFIG_CMD_BDI
240 #define CONFIG_CMD_DHCP
241 #define CONFIG_CMD_ENV
242 #define CONFIG_CMD_FLASH
243 #define CONFIG_CMD_IMI
244 #define CONFIG_CMD_MEMORY
245 #define CONFIG_CMD_MII
246 #define CONFIG_CMD_NET
247 #define CONFIG_CMD_PING
248 #define CONFIG_CMD_SAVEENV
249 #define CONFIG_CMD_RUN
250 #define CONFIG_CMD_BOOTD
251 #define CONFIG_CMD_ECHO
252 #define CONFIG_CMD_SOURCE
253 #define CONFIG_CMD_FAT
254 #define CONFIG_DOS_PARTITION
256 /* Miscellaneous configurable options */
257 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
258 #define CONFIG_ARCH_EARLY_INIT_R
260 /* Physical Memory Map */
261 /* fixme: these need to be checked against the board */
262 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
263 #define CONFIG_SYS_CLK_FREQ 100000000
264 #define CONFIG_DDR_CLK_FREQ 133333333
266 #define CONFIG_NR_DRAM_BANKS 3
268 #define CONFIG_HWCONFIG
269 #define HWCONFIG_BUFFER_SIZE 128
271 #define CONFIG_DISPLAY_CPUINFO
273 /* Initial environment variables */
274 #define CONFIG_EXTRA_ENV_SETTINGS \
275 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
276 "loadaddr=0x80100000\0" \
277 "kernel_addr=0x100000\0" \
278 "ramdisk_addr=0x800000\0" \
279 "ramdisk_size=0x2000000\0" \
280 "fdt_high=0xffffffffffffffff\0" \
281 "initrd_high=0xffffffffffffffff\0" \
282 "kernel_start=0x581200000\0" \
283 "kernel_load=0xa0000000\0" \
284 "kernel_size=0x1000000\0" \
285 "console=ttyAMA0,38400n8\0"
287 #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
288 "earlycon=uart8250,mmio,0x21c0600,115200 " \
289 "default_hugepagesz=2m hugepagesz=2m " \
291 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
292 "$kernel_size && bootm $kernel_load"
293 #define CONFIG_BOOTDELAY 1
295 /* Store environment at top of flash */
296 #define CONFIG_ENV_IS_NOWHERE 1
297 #define CONFIG_ENV_SIZE 0x1000
299 /* Monitor Command Prompt */
300 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
301 #define CONFIG_SYS_PROMPT "> "
302 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
303 sizeof(CONFIG_SYS_PROMPT) + 16)
304 #define CONFIG_SYS_HUSH_PARSER
305 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
306 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
307 #define CONFIG_SYS_LONGHELP
308 #define CONFIG_CMDLINE_EDITING 1
309 #define CONFIG_SYS_MAXARGS 64 /* max command args */
312 unsigned long get_dram_size_to_hide(void);
315 #endif /* __LS2_COMMON_H */