include/configs/ls2085a_common.h

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS2_COMMON_H
   8 #define __LS2_COMMON_H
   9
  10 #define CONFIG_SYS_GENERIC_BOARD
  11
  12 #define CONFIG_REMAKE_ELF
  13 #define CONFIG_FSL_LSCH3
  14 #define CONFIG_LS2085A
  15 #define CONFIG_GICV3
  16 #define CONFIG_FSL_TZPC_BP147
  17
  18 /* Link Definitions */
  19 #define CONFIG_SYS_TEXT_BASE            0x30001000
  20
  21 #ifdef CONFIG_EMU
  22 #define CONFIG_SYS_NO_FLASH
  23 #endif
  24
  25 #define CONFIG_SUPPORT_RAW_INITRD
  26
  27 #define CONFIG_SKIP_LOWLEVEL_INIT
  28 #define CONFIG_BOARD_EARLY_INIT_F       1
  29
  30 #define CONFIG_IDENT_STRING             " LS2085A-EMU"
  31 #define CONFIG_BOOTP_VCI_STRING         "U-boot.LS2085A-EMU"
  32
  33 /* Flat Device Tree Definitions */
  34 #define CONFIG_OF_LIBFDT
  35 #define CONFIG_OF_BOARD_SETUP
  36
  37 /* new uImage format support */
  38 #define CONFIG_FIT
  39 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
  40
  41 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  42 #ifndef CONFIG_SYS_FSL_DDR4
  43 #define CONFIG_SYS_FSL_DDR3             /* Use DDR3 memory */
  44 #define CONFIG_SYS_DDR_RAW_TIMING
  45 #endif
  46 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  47 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  48
  49 #define CONFIG_SYS_FSL_DDR_INTLV_256B   /* force 256 byte interleaving */
  50
  51 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  52 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  53 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  54 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x8080000000ULL
  55 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS       2
  56
  57 /*
  58  * SMP Definitinos
  59  */
  60 #define CPU_RELEASE_ADDR                secondary_boot_func
  61
  62 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
  63 #define CONFIG_SYS_DP_DDR_BASE          0x6000000000ULL
  64 /*
  65  * DDR controller use 0 as the base address for binding.
  66  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
  67  */
  68 #define CONFIG_SYS_DP_DDR_BASE_PHY      0
  69 #define CONFIG_DP_DDR_CTRL              2
  70 #define CONFIG_DP_DDR_NUM_CTRLS         1
  71 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  72
  73 /* Generic Timer Definitions */
  74 #define COUNTER_FREQUENCY               12000000        /* 12MHz */
  75
  76 /* Size of malloc() pool */
  77 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128 * 1024)
  78
  79 /* I2C */
  80 #define CONFIG_CMD_I2C
  81 #define CONFIG_SYS_I2C
  82 #define CONFIG_SYS_I2C_MXC
  83 #define CONFIG_SYS_MXC_I2C1_SPEED       40000000
  84 #define CONFIG_SYS_MXC_I2C2_SPEED       40000000
  85
  86 /* Serial Port */
  87 #define CONFIG_CONS_INDEX       2
  88 #define CONFIG_SYS_NS16550
  89 #define CONFIG_SYS_NS16550_SERIAL
  90 #define CONFIG_SYS_NS16550_REG_SIZE     1
  91 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
  92
  93 #define CONFIG_BAUDRATE                 115200
  94 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  95
  96 /* IFC */
  97 #define CONFIG_FSL_IFC
  98 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  99 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 100 /*
 101  * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
 102  * address 0. But this region is limited to 256MB. To accommodate bigger NOR
 103  * flash and other devices, we will map CS0 to 0x580000000 after relocation.
 104  * CONFIG_SYS_FLASH_BASE has the final address (core view)
 105  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 106  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 107  * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
 108  */
 109 #define CONFIG_SYS_FLASH_BASE                   0x580000000ULL
 110 #define CONFIG_SYS_FLASH_BASE_PHYS              0x80000000
 111 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 112
 113 /*
 114  * NOR Flash Timing Params
 115  */
 116 #define CONFIG_SYS_NOR0_CSPR                                    \
 117         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
 118         CSPR_PORT_SIZE_16                                       | \
 119         CSPR_MSEL_NOR                                           | \
 120         CSPR_V)
 121 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
 122         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
 123         CSPR_PORT_SIZE_16                                       | \
 124         CSPR_MSEL_NOR                                           | \
 125         CSPR_V)
 126 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
 127 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
 128                                 FTIM0_NOR_TEADC(0x1) | \
 129                                 FTIM0_NOR_TEAHC(0x1))
 130 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
 131                                 FTIM1_NOR_TRAD_NOR(0x1))
 132 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
 133                                 FTIM2_NOR_TCH(0x0) | \
 134                                 FTIM2_NOR_TWP(0x1))
 135 #define CONFIG_SYS_NOR_FTIM3    0x04000000
 136 #define CONFIG_SYS_IFC_CCR      0x01000000
 137
 138 #ifndef CONFIG_SYS_NO_FLASH
 139 #define CONFIG_FLASH_CFI_DRIVER
 140 #define CONFIG_SYS_FLASH_CFI
 141 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 142 #define CONFIG_SYS_FLASH_QUIET_TEST
 143 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 144
 145 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 146 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 147 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 148 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 149
 150 #define CONFIG_SYS_FLASH_EMPTY_INFO
 151 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 152 #endif
 153
 154 #define CONFIG_NAND_FSL_IFC
 155 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 156 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 157 #define CONFIG_SYS_NAND_BASE            0x520000000
 158 #define CONFIG_SYS_NAND_BASE_PHYS       0x20000000
 159
 160 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 161 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 162                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 163                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 164                                 | CSPR_V)
 165 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 166
 167 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 168                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 169                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 170                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 171                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 172                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 173                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 174
 175 #define CONFIG_SYS_NAND_ONFI_DETECTION
 176
 177 /* ONFI NAND Flash mode0 Timing Params */
 178 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 179                                         FTIM0_NAND_TWP(0x18)   | \
 180                                         FTIM0_NAND_TWCHT(0x07) | \
 181                                         FTIM0_NAND_TWH(0x0a))
 182 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 183                                         FTIM1_NAND_TWBE(0x39)  | \
 184                                         FTIM1_NAND_TRR(0x0e)   | \
 185                                         FTIM1_NAND_TRP(0x18))
 186 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 187                                         FTIM2_NAND_TREH(0x0a) | \
 188                                         FTIM2_NAND_TWHRE(0x1e))
 189 #define CONFIG_SYS_NAND_FTIM3           0x0
 190
 191 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 192 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 193 #define CONFIG_MTD_NAND_VERIFY_WRITE
 194 #define CONFIG_CMD_NAND
 195
 196 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 197
 198 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 199 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 200 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 201 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 202 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 203 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 204 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 205 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 206 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 207
 208 /* MC firmware */
 209 #define CONFIG_FSL_MC_ENET
 210 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE    (512UL * 1024 * 1024)
 211 #define CONFIG_SYS_LS_MC_FW_IN_NOR
 212 #define CONFIG_SYS_LS_MC_FW_ADDR        0x580200000ULL
 213 /* TODO Actual FW length needs to be determined at runtime from FW header */
 214 #define CONFIG_SYS_LS_MC_FW_LENGTH      (4U * 1024 * 1024)
 215 #define CONFIG_SYS_LS_MC_DPL_IN_NOR
 216 #define CONFIG_SYS_LS_MC_DPL_ADDR       0x5806C0000ULL
 217 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
 218 #define CONFIG_SYS_LS_MC_DPL_LENGTH     4096
 219 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0xe00000
 220
 221 /* Carve the MC private DRAM block from the end of DRAM */
 222 #ifdef CONFIG_FSL_MC_ENET
 223 #define CONFIG_SYS_MEM_TOP_HIDE         mc_get_dram_block_size()
 224 #endif
 225
 226 /* Command line configuration */
 227 #define CONFIG_CMD_CACHE
 228 #define CONFIG_CMD_BDI
 229 #define CONFIG_CMD_DHCP
 230 #define CONFIG_CMD_ENV
 231 #define CONFIG_CMD_FLASH
 232 #define CONFIG_CMD_IMI
 233 #define CONFIG_CMD_MEMORY
 234 #define CONFIG_CMD_MII
 235 #define CONFIG_CMD_NET
 236 #define CONFIG_CMD_PING
 237 #define CONFIG_CMD_SAVEENV
 238 #define CONFIG_CMD_RUN
 239 #define CONFIG_CMD_BOOTD
 240 #define CONFIG_CMD_ECHO
 241 #define CONFIG_CMD_SOURCE
 242 #define CONFIG_CMD_FAT
 243 #define CONFIG_DOS_PARTITION
 244
 245 /* Miscellaneous configurable options */
 246 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 247 #define CONFIG_ARCH_EARLY_INIT_R
 248
 249 /* Physical Memory Map */
 250 /* fixme: these need to be checked against the board */
 251 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 252 #define CONFIG_SYS_CLK_FREQ     100000000
 253 #define CONFIG_DDR_CLK_FREQ     133333333
 254
 255
 256 #define CONFIG_NR_DRAM_BANKS            3
 257
 258 #define CONFIG_HWCONFIG
 259 #define HWCONFIG_BUFFER_SIZE            128
 260
 261 #define CONFIG_DISPLAY_CPUINFO
 262
 263 /* Initial environment variables */
 264 #define CONFIG_EXTRA_ENV_SETTINGS               \
 265         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 266         "loadaddr=0x80100000\0"                 \
 267         "kernel_addr=0x100000\0"                \
 268         "ramdisk_addr=0x800000\0"               \
 269         "ramdisk_size=0x2000000\0"              \
 270         "fdt_high=0xffffffffffffffff\0"         \
 271         "initrd_high=0xffffffffffffffff\0"      \
 272         "kernel_start=0x581200000\0"            \
 273         "kernel_load=0x806f0000\0"              \
 274         "kernel_size=0x1000000\0"               \
 275         "console=ttyAMA0,38400n8\0"
 276
 277 #define CONFIG_BOOTARGS         "console=ttyS1,115200 root=/dev/ram0 " \
 278                                 "earlycon=uart8250,mmio,0x21c0600,115200 " \
 279                                 "default_hugepagesz=2m hugepagesz=2m " \
 280                                 "hugepages=16"
 281 #define CONFIG_BOOTCOMMAND              "cp.b $kernel_start $kernel_load "     \
 282                                         "$kernel_size && bootm $kernel_load"
 283 #define CONFIG_BOOTDELAY                1
 284
 285 /* Store environment at top of flash */
 286 #define CONFIG_ENV_IS_NOWHERE           1
 287 #define CONFIG_ENV_SIZE                 0x1000
 288
 289 /* Monitor Command Prompt */
 290 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 291 #define CONFIG_SYS_PROMPT               "> "
 292 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 293                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 294 #define CONFIG_SYS_HUSH_PARSER
 295 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 296 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 297 #define CONFIG_SYS_LONGHELP
 298 #define CONFIG_CMDLINE_EDITING          1
 299 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 300
 301 #ifndef __ASSEMBLY__
 302 unsigned long mc_get_dram_block_size(void);
 303 #endif
 304
 305 #endif /* __LS2_COMMON_H */