include/configs/ls2080ardb.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS2_RDB_H
   8 #define __LS2_RDB_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #undef CONFIG_CONS_INDEX
  13 #define CONFIG_CONS_INDEX       2
  14
  15 #define CONFIG_DISPLAY_BOARDINFO
  16
  17 #ifndef __ASSEMBLY__
  18 unsigned long get_board_sys_clk(void);
  19 #endif
  20
  21 #define CONFIG_SYS_FSL_CLK
  22 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  23 #define CONFIG_DDR_CLK_FREQ             133333333
  24 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  25
  26 #define CONFIG_DDR_SPD
  27 #define CONFIG_DDR_ECC
  28 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  29 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  30 #define SPD_EEPROM_ADDRESS1     0x51
  31 #define SPD_EEPROM_ADDRESS2     0x52
  32 #define SPD_EEPROM_ADDRESS3     0x53
  33 #define SPD_EEPROM_ADDRESS4     0x54
  34 #define SPD_EEPROM_ADDRESS5     0x55
  35 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  36 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  37 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  38 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  39 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  40 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  41 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  42 #endif
  43 #define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
  44
  45 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
  46
  47 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  48 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  49 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  50
  51 #define CONFIG_SYS_NOR0_CSPR                                    \
  52         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  53         CSPR_PORT_SIZE_16                                       | \
  54         CSPR_MSEL_NOR                                           | \
  55         CSPR_V)
  56 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  57         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  58         CSPR_PORT_SIZE_16                                       | \
  59         CSPR_MSEL_NOR                                           | \
  60         CSPR_V)
  61 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  62 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  63                                 FTIM0_NOR_TEADC(0x5) | \
  64                                 FTIM0_NOR_TEAHC(0x5))
  65 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  66                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  67                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  68 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  69                                 FTIM2_NOR_TCH(0x4) | \
  70                                 FTIM2_NOR_TWPH(0x0E) | \
  71                                 FTIM2_NOR_TWP(0x1c))
  72 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  73 #define CONFIG_SYS_IFC_CCR      0x01000000
  74
  75 #ifndef CONFIG_SYS_NO_FLASH
  76 #define CONFIG_FLASH_CFI_DRIVER
  77 #define CONFIG_SYS_FLASH_CFI
  78 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  79 #define CONFIG_SYS_FLASH_QUIET_TEST
  80 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  81
  82 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  83 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  84 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  85 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  86
  87 #define CONFIG_SYS_FLASH_EMPTY_INFO
  88 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  89                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  90 #endif
  91
  92 #define CONFIG_NAND_FSL_IFC
  93 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  94 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  95
  96
  97 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  98 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  99                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 100                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 101                                 | CSPR_V)
 102 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 103
 104 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 105                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 106                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 107                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 108                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 109                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 110                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
 111
 112 #define CONFIG_SYS_NAND_ONFI_DETECTION
 113
 114 /* ONFI NAND Flash mode0 Timing Params */
 115 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
 116                                         FTIM0_NAND_TWP(0x30)   | \
 117                                         FTIM0_NAND_TWCHT(0x0e) | \
 118                                         FTIM0_NAND_TWH(0x14))
 119 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
 120                                         FTIM1_NAND_TWBE(0xab)  | \
 121                                         FTIM1_NAND_TRR(0x1c)   | \
 122                                         FTIM1_NAND_TRP(0x30))
 123 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
 124                                         FTIM2_NAND_TREH(0x14) | \
 125                                         FTIM2_NAND_TWHRE(0x3c))
 126 #define CONFIG_SYS_NAND_FTIM3           0x0
 127
 128 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 129 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 130 #define CONFIG_MTD_NAND_VERIFY_WRITE
 131 #define CONFIG_CMD_NAND
 132
 133 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 134
 135 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 136 #define QIXIS_LBMAP_SWITCH              0x06
 137 #define QIXIS_LBMAP_MASK                0x0f
 138 #define QIXIS_LBMAP_SHIFT               0
 139 #define QIXIS_LBMAP_DFLTBANK            0x00
 140 #define QIXIS_LBMAP_ALTBANK             0x04
 141 #define QIXIS_LBMAP_NAND                0x09
 142 #define QIXIS_RST_CTL_RESET             0x31
 143 #define QIXIS_RST_CTL_RESET_EN          0x30
 144 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 145 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 146 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 147 #define QIXIS_RCW_SRC_NAND              0x119
 148 #define QIXIS_RST_FORCE_MEM             0x01
 149
 150 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 151 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 152                                 | CSPR_PORT_SIZE_8 \
 153                                 | CSPR_MSEL_GPCM \
 154                                 | CSPR_V)
 155 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 156                                 | CSPR_PORT_SIZE_8 \
 157                                 | CSPR_MSEL_GPCM \
 158                                 | CSPR_V)
 159
 160 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 161 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 162 /* QIXIS Timing parameters for IFC CS3 */
 163 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 164                                         FTIM0_GPCM_TEADC(0x0e) | \
 165                                         FTIM0_GPCM_TEAHC(0x0e))
 166 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 167                                         FTIM1_GPCM_TRAD(0x3f))
 168 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 169                                         FTIM2_GPCM_TCH(0xf) | \
 170                                         FTIM2_GPCM_TWP(0x3E))
 171 #define CONFIG_SYS_CS3_FTIM3            0x0
 172
 173 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
 174 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 175 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
 176 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
 177 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 178 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 179 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 180 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 181 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 182 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 183 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 184 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 185 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 186 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 187 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 188 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 189 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 190 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 191
 192 #define CONFIG_ENV_IS_IN_NAND
 193 #define CONFIG_ENV_OFFSET               (2048 * 1024)
 194 #define CONFIG_ENV_SECT_SIZE            0x20000
 195 #define CONFIG_ENV_SIZE                 0x2000
 196 #define CONFIG_SPL_PAD_TO               0x80000
 197 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (1024 * 1024)
 198 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
 199 #else
 200 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 201 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 202 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 203 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 204 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 205 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 206 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 207 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 208 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 209 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 210 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 211 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 212 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 213 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 214 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 215 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 216 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 217
 218 #define CONFIG_ENV_IS_IN_FLASH
 219 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
 220 #define CONFIG_ENV_SECT_SIZE            0x20000
 221 #define CONFIG_ENV_SIZE                 0x2000
 222 #endif
 223
 224 /* Debug Server firmware */
 225 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 226 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 227
 228 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 229
 230 /*
 231  * I2C
 232  */
 233 #define I2C_MUX_PCA_ADDR                0x75
 234 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
 235
 236 /* I2C bus multiplexer */
 237 #define I2C_MUX_CH_DEFAULT      0x8
 238
 239 /* SPI */
 240 #ifdef CONFIG_FSL_DSPI
 241 #define CONFIG_CMD_SF
 242 #define CONFIG_SPI_FLASH
 243 #define CONFIG_SPI_FLASH_BAR
 244 #endif
 245
 246 /*
 247  * RTC configuration
 248  */
 249 #define RTC
 250 #define CONFIG_RTC_DS3231               1
 251 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 252 #define CONFIG_CMD_DATE
 253
 254 /* EEPROM */
 255 #define CONFIG_ID_EEPROM
 256 #define CONFIG_CMD_EEPROM
 257 #define CONFIG_SYS_I2C_EEPROM_NXID
 258 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 259 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 260 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 261 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 262 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 263
 264 #define CONFIG_FSL_MEMAC
 265 #define CONFIG_PCI              /* Enable PCIE */
 266 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 267
 268 #ifdef CONFIG_PCI
 269 #define CONFIG_PCI_PNP
 270 #define CONFIG_PCI_SCAN_SHOW
 271 #define CONFIG_CMD_PCI
 272 #endif
 273
 274 /*  MMC  */
 275 #define CONFIG_MMC
 276 #ifdef CONFIG_MMC
 277 #define CONFIG_CMD_MMC
 278 #define CONFIG_FSL_ESDHC
 279 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 280 #define CONFIG_GENERIC_MMC
 281 #define CONFIG_CMD_FAT
 282 #define CONFIG_DOS_PARTITION
 283 #endif
 284
 285 #define CONFIG_MISC_INIT_R
 286
 287 /*
 288  * USB
 289  */
 290 #define CONFIG_HAS_FSL_XHCI_USB
 291 #define CONFIG_USB_XHCI
 292 #define CONFIG_USB_XHCI_FSL
 293 #define CONFIG_USB_XHCI_DWC3
 294 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
 295 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 296 #define CONFIG_CMD_USB
 297 #define CONFIG_USB_STORAGE
 298 #define CONFIG_CMD_EXT2
 299
 300 /* Initial environment variables */
 301 #undef CONFIG_EXTRA_ENV_SETTINGS
 302 #define CONFIG_EXTRA_ENV_SETTINGS               \
 303         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 304         "loadaddr=0x80100000\0"                 \
 305         "kernel_addr=0x100000\0"                \
 306         "ramdisk_addr=0x800000\0"               \
 307         "ramdisk_size=0x2000000\0"              \
 308         "fdt_high=0xa0000000\0"                 \
 309         "initrd_high=0xffffffffffffffff\0"      \
 310         "kernel_start=0x581100000\0"            \
 311         "kernel_load=0xa0000000\0"              \
 312         "kernel_size=0x2800000\0"
 313
 314 #undef CONFIG_BOOTARGS
 315 #define CONFIG_BOOTARGS         "console=ttyS1,115200 root=/dev/ram0 " \
 316                                 "earlycon=uart8250,mmio,0x21c0600,115200 " \
 317                                 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
 318                                 " hugepagesz=2m hugepages=16"
 319
 320 /* MAC/PHY configuration */
 321 #ifdef CONFIG_FSL_MC_ENET
 322 #define CONFIG_PHYLIB_10G
 323 #define CONFIG_PHY_AQUANTIA
 324 #define CONFIG_PHY_CORTINA
 325 #define CONFIG_PHYLIB
 326 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 327 #define CONFIG_CORTINA_FW_ADDR          0x581000000
 328 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 329
 330 #define CORTINA_PHY_ADDR1       0x10
 331 #define CORTINA_PHY_ADDR2       0x11
 332 #define CORTINA_PHY_ADDR3       0x12
 333 #define CORTINA_PHY_ADDR4       0x13
 334 #define AQ_PHY_ADDR1            0x00
 335 #define AQ_PHY_ADDR2            0x01
 336 #define AQ_PHY_ADDR3            0x02
 337 #define AQ_PHY_ADDR4            0x03
 338
 339 #define CONFIG_MII
 340 #define CONFIG_ETHPRIME         "DPNI1"
 341 #define CONFIG_PHY_GIGE
 342 #define CONFIG_PHY_AQUANTIA
 343 #endif
 344
 345 #endif /* __LS2_RDB_H */