1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2019-2021 NXP
4 * Copyright 2015 Freescale Semiconductor
10 #include "ls2080a_common.h"
12 #define I2C_MUX_CH_VOL_MONITOR 0xa
13 #define I2C_VOL_MONITOR_ADDR 0x38
15 /* step the IR regulator in 5mV increments */
16 #define IR_VDD_STEP_DOWN 5
17 #define IR_VDD_STEP_UP 5
18 /* The lowest and highest voltage allowed for LS2080ARDB */
19 #define VDD_MV_MIN 819
20 #define VDD_MV_MAX 1212
22 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
24 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
25 #define SPD_EEPROM_ADDRESS1 0x51
26 #define SPD_EEPROM_ADDRESS2 0x52
27 #define SPD_EEPROM_ADDRESS3 0x53
28 #define SPD_EEPROM_ADDRESS4 0x54
29 #define SPD_EEPROM_ADDRESS5 0x55
30 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
31 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
33 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
35 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
36 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
37 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
39 #define CONFIG_SYS_NOR0_CSPR \
40 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
44 #define CONFIG_SYS_NOR0_CSPR_EARLY \
45 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
49 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
50 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
51 FTIM0_NOR_TEADC(0x5) | \
53 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
54 FTIM1_NOR_TRAD_NOR(0x1a) |\
55 FTIM1_NOR_TSEQRAD_NOR(0x13))
56 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
57 FTIM2_NOR_TCH(0x4) | \
58 FTIM2_NOR_TWPH(0x0E) | \
60 #define CONFIG_SYS_NOR_FTIM3 0x04000000
61 #define CONFIG_SYS_IFC_CCR 0x01000000
63 #ifdef CONFIG_MTD_NOR_FLASH
64 #define CONFIG_SYS_FLASH_QUIET_TEST
65 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
67 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
69 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
70 CONFIG_SYS_FLASH_BASE + 0x40000000}
73 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
74 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
76 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
77 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
78 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
79 | CSPR_MSEL_NAND /* MSEL = NAND */ \
81 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
83 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
84 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
85 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
86 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
87 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
88 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
89 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
91 /* ONFI NAND Flash mode0 Timing Params */
92 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
93 FTIM0_NAND_TWP(0x30) | \
94 FTIM0_NAND_TWCHT(0x0e) | \
96 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
97 FTIM1_NAND_TWBE(0xab) | \
98 FTIM1_NAND_TRR(0x1c) | \
100 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
101 FTIM2_NAND_TREH(0x14) | \
102 FTIM2_NAND_TWHRE(0x3c))
103 #define CONFIG_SYS_NAND_FTIM3 0x0
105 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
106 #define CONFIG_SYS_MAX_NAND_DEVICE 1
107 #define CONFIG_MTD_NAND_VERIFY_WRITE
109 #define QIXIS_LBMAP_SWITCH 0x06
110 #define QIXIS_LBMAP_MASK 0x0f
111 #define QIXIS_LBMAP_SHIFT 0
112 #define QIXIS_LBMAP_DFLTBANK 0x00
113 #define QIXIS_LBMAP_ALTBANK 0x04
114 #define QIXIS_LBMAP_NAND 0x09
115 #define QIXIS_RST_CTL_RESET 0x31
116 #define QIXIS_RST_CTL_RESET_EN 0x30
117 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
118 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
119 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
120 #define QIXIS_RCW_SRC_NAND 0x119
121 #define QIXIS_RST_FORCE_MEM 0x01
123 #define CONFIG_SYS_CSPR3_EXT (0x0)
124 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
128 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
133 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
134 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
135 /* QIXIS Timing parameters for IFC CS3 */
136 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
137 FTIM0_GPCM_TEADC(0x0e) | \
138 FTIM0_GPCM_TEAHC(0x0e))
139 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
140 FTIM1_GPCM_TRAD(0x3f))
141 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
142 FTIM2_GPCM_TCH(0xf) | \
143 FTIM2_GPCM_TWP(0x3E))
144 #define CONFIG_SYS_CS3_FTIM3 0x0
146 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
147 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
148 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
149 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
150 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
151 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
152 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
153 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
154 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
155 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
156 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
157 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
158 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
159 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
160 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
161 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
162 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
163 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
165 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
167 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
168 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
169 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
170 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
171 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
172 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
173 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
174 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
175 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
176 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
177 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
178 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
179 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
180 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
181 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
182 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
183 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
186 /* Debug Server firmware */
187 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
188 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
190 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
192 #ifdef CONFIG_TARGET_LS2081ARDB
193 #define QIXIS_QMAP_MASK 0x07
194 #define QIXIS_QMAP_SHIFT 5
195 #define QIXIS_LBMAP_DFLTBANK 0x00
196 #define QIXIS_LBMAP_QSPI 0x00
197 #define QIXIS_RCW_SRC_QSPI 0x62
198 #define QIXIS_LBMAP_ALTBANK 0x20
199 #define QIXIS_RST_CTL_RESET 0x31
200 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
201 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
202 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
203 #define QIXIS_LBMAP_MASK 0x0f
204 #define QIXIS_RST_CTL_RESET_EN 0x30
210 #ifdef CONFIG_TARGET_LS2081ARDB
211 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
213 #define I2C_MUX_PCA_ADDR 0x75
214 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
216 /* I2C bus multiplexer */
217 #define I2C_MUX_CH_DEFAULT 0x8
225 #ifdef CONFIG_TARGET_LS2081ARDB
226 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
228 #define CONFIG_RTC_DS3231 1
229 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
233 #define CONFIG_SYS_I2C_EEPROM_NXID
234 #define CONFIG_SYS_EEPROM_BUS_NUM 0
236 #define CONFIG_FSL_MEMAC
238 #define BOOT_TARGET_DEVICES(func) \
241 func(SCSI, scsi, 0) \
243 #include <config_distro_bootcmd.h>
245 #ifdef CONFIG_TFABOOT
246 #define QSPI_MC_INIT_CMD \
248 "sf read 0x80640000 0x640000 0x80000; " \
249 "env exists secureboot && " \
250 "esbc_validate 0x80640000 && " \
251 "esbc_validate 0x80680000; " \
252 "sf read 0x80a00000 0xa00000 0x200000; " \
253 "sf read 0x80e00000 0xe00000 0x100000; " \
254 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
255 #define SD_MC_INIT_CMD \
256 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
257 "mmc read 0x80e00000 0x7000 0x800;" \
258 "env exists secureboot && " \
259 "mmc read 0x80640000 0x3200 0x20 && " \
260 "mmc read 0x80680000 0x3400 0x20 && " \
261 "esbc_validate 0x80640000 && " \
262 "esbc_validate 0x80680000 ;" \
263 "fsl_mc start mc 0x80a00000 0x80e00000\0"
264 #define IFC_MC_INIT_CMD \
265 "env exists secureboot && " \
266 "esbc_validate 0x580640000 && " \
267 "esbc_validate 0x580680000; " \
268 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
270 #ifdef CONFIG_QSPI_BOOT
271 #define MC_INIT_CMD \
272 "mcinitcmd=sf probe 0:0; " \
273 "sf read 0x80640000 0x640000 0x80000; " \
274 "env exists secureboot && " \
275 "esbc_validate 0x80640000 && " \
276 "esbc_validate 0x80680000; " \
277 "sf read 0x80a00000 0xa00000 0x200000; " \
278 "sf read 0x80e00000 0xe00000 0x100000; " \
279 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
280 #elif defined(CONFIG_SD_BOOT)
281 #define MC_INIT_CMD \
282 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
283 "mmc read 0x80e00000 0x7000 0x800;" \
284 "env exists secureboot && " \
285 "mmc read 0x80640000 0x3200 0x20 && " \
286 "mmc read 0x80680000 0x3400 0x20 && " \
287 "esbc_validate 0x80640000 && " \
288 "esbc_validate 0x80680000 ;" \
289 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
290 "mcmemsize=0x70000000\0"
292 #define MC_INIT_CMD \
293 "mcinitcmd=env exists secureboot && " \
294 "esbc_validate 0x580640000 && " \
295 "esbc_validate 0x580680000; " \
296 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
300 /* Initial environment variables */
301 #undef CONFIG_EXTRA_ENV_SETTINGS
302 #ifdef CONFIG_TFABOOT
303 #define CONFIG_EXTRA_ENV_SETTINGS \
304 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
305 "ramdisk_addr=0x800000\0" \
306 "ramdisk_size=0x2000000\0" \
307 "fdt_high=0xa0000000\0" \
308 "initrd_high=0xffffffffffffffff\0" \
309 "kernel_addr=0x581000000\0" \
310 "kernel_start=0x1000000\0" \
311 "kernelheader_start=0x800000\0" \
312 "scriptaddr=0x80000000\0" \
313 "scripthdraddr=0x80080000\0" \
314 "fdtheader_addr_r=0x80100000\0" \
315 "kernelheader_addr_r=0x80200000\0" \
316 "kernelheader_addr=0x580600000\0" \
317 "kernel_addr_r=0x81000000\0" \
318 "kernelheader_size=0x40000\0" \
319 "fdt_addr_r=0x90000000\0" \
320 "load_addr=0xa0000000\0" \
321 "kernel_size=0x2800000\0" \
322 "kernel_addr_sd=0x8000\0" \
323 "kernel_size_sd=0x14000\0" \
324 "console=ttyAMA0,38400n8\0" \
325 "mcmemsize=0x70000000\0" \
326 "sd_bootcmd=echo Trying load from SD ..;" \
327 "mmcinfo; mmc read $load_addr " \
328 "$kernel_addr_sd $kernel_size_sd && " \
329 "bootm $load_addr#$board\0" \
332 "boot_scripts=ls2088ardb_boot.scr\0" \
333 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
334 "scan_dev_for_boot_part=" \
335 "part list ${devtype} ${devnum} devplist; " \
336 "env exists devplist || setenv devplist 1; " \
337 "for distro_bootpart in ${devplist}; do " \
338 "if fstype ${devtype} " \
339 "${devnum}:${distro_bootpart} " \
340 "bootfstype; then " \
341 "run scan_dev_for_boot; " \
345 "load ${devtype} ${devnum}:${distro_bootpart} " \
346 "${scriptaddr} ${prefix}${script}; " \
347 "env exists secureboot && load ${devtype} " \
348 "${devnum}:${distro_bootpart} " \
349 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
350 "&& esbc_validate ${scripthdraddr};" \
351 "source ${scriptaddr}\0" \
352 "qspi_bootcmd=echo Trying load from qspi..;" \
353 "sf probe && sf read $load_addr " \
354 "$kernel_start $kernel_size ; env exists secureboot &&" \
355 "sf read $kernelheader_addr_r $kernelheader_start " \
356 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
357 " bootm $load_addr#$board\0" \
358 "nor_bootcmd=echo Trying load from nor..;" \
359 "cp.b $kernel_addr $load_addr " \
360 "$kernel_size ; env exists secureboot && " \
361 "cp.b $kernelheader_addr $kernelheader_addr_r " \
362 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
363 "bootm $load_addr#$board\0"
365 #define CONFIG_EXTRA_ENV_SETTINGS \
366 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
367 "ramdisk_addr=0x800000\0" \
368 "ramdisk_size=0x2000000\0" \
369 "fdt_high=0xa0000000\0" \
370 "initrd_high=0xffffffffffffffff\0" \
371 "kernel_addr=0x581000000\0" \
372 "kernel_start=0x1000000\0" \
373 "kernelheader_start=0x600000\0" \
374 "scriptaddr=0x80000000\0" \
375 "scripthdraddr=0x80080000\0" \
376 "fdtheader_addr_r=0x80100000\0" \
377 "kernelheader_addr_r=0x80200000\0" \
378 "kernelheader_addr=0x580600000\0" \
379 "kernel_addr_r=0x81000000\0" \
380 "kernelheader_size=0x40000\0" \
381 "fdt_addr_r=0x90000000\0" \
382 "load_addr=0xa0000000\0" \
383 "kernel_size=0x2800000\0" \
384 "kernel_addr_sd=0x8000\0" \
385 "kernel_size_sd=0x14000\0" \
386 "console=ttyAMA0,38400n8\0" \
387 "mcmemsize=0x70000000\0" \
388 "sd_bootcmd=echo Trying load from SD ..;" \
389 "mmcinfo; mmc read $load_addr " \
390 "$kernel_addr_sd $kernel_size_sd && " \
391 "bootm $load_addr#$board\0" \
394 "boot_scripts=ls2088ardb_boot.scr\0" \
395 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
396 "scan_dev_for_boot_part=" \
397 "part list ${devtype} ${devnum} devplist; " \
398 "env exists devplist || setenv devplist 1; " \
399 "for distro_bootpart in ${devplist}; do " \
400 "if fstype ${devtype} " \
401 "${devnum}:${distro_bootpart} " \
402 "bootfstype; then " \
403 "run scan_dev_for_boot; " \
407 "load ${devtype} ${devnum}:${distro_bootpart} " \
408 "${scriptaddr} ${prefix}${script}; " \
409 "env exists secureboot && load ${devtype} " \
410 "${devnum}:${distro_bootpart} " \
411 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
412 "env exists secureboot " \
413 "&& esbc_validate ${scripthdraddr};" \
414 "source ${scriptaddr}\0" \
415 "qspi_bootcmd=echo Trying load from qspi..;" \
416 "sf probe && sf read $load_addr " \
417 "$kernel_start $kernel_size ; env exists secureboot &&" \
418 "sf read $kernelheader_addr_r $kernelheader_start " \
419 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
420 " bootm $load_addr#$board\0" \
421 "nor_bootcmd=echo Trying load from nor..;" \
422 "cp.b $kernel_addr $load_addr " \
423 "$kernel_size ; env exists secureboot && " \
424 "cp.b $kernelheader_addr $kernelheader_addr_r " \
425 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
426 "bootm $load_addr#$board\0"
429 #ifdef CONFIG_TFABOOT
430 #define QSPI_NOR_BOOTCOMMAND \
432 "sf read 0x806c0000 0x6c0000 0x40000; " \
433 "env exists mcinitcmd && env exists secureboot "\
434 "&& esbc_validate 0x806c0000; " \
435 "sf read 0x80d00000 0xd00000 0x100000; " \
436 "env exists mcinitcmd && " \
437 "fsl_mc lazyapply dpl 0x80d00000; " \
438 "run distro_bootcmd;run qspi_bootcmd; " \
439 "env exists secureboot && esbc_halt;"
441 /* Try to boot an on-SD kernel first, then do normal distro boot */
442 #define SD_BOOTCOMMAND \
443 "env exists mcinitcmd && env exists secureboot "\
444 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
445 "&& esbc_validate $load_addr; " \
446 "env exists mcinitcmd && run mcinitcmd " \
447 "&& mmc read 0x80d00000 0x6800 0x800 " \
448 "&& fsl_mc lazyapply dpl 0x80d00000; " \
449 "run distro_bootcmd;run sd_bootcmd; " \
450 "env exists secureboot && esbc_halt;"
452 /* Try to boot an on-NOR kernel first, then do normal distro boot */
453 #define IFC_NOR_BOOTCOMMAND \
454 "env exists mcinitcmd && env exists secureboot "\
455 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
456 "&& fsl_mc lazyapply dpl 0x580d00000;" \
457 "run distro_bootcmd;run nor_bootcmd; " \
458 "env exists secureboot && esbc_halt;"
460 #ifdef CONFIG_QSPI_BOOT
461 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
462 #elif defined(CONFIG_SD_BOOT)
463 /* Try to boot an on-SD kernel first, then do normal distro boot */
465 /* Try to boot an on-NOR kernel first, then do normal distro boot */
469 /* MAC/PHY configuration */
470 #define CORTINA_PHY_ADDR1 0x10
471 #define CORTINA_PHY_ADDR2 0x11
472 #define CORTINA_PHY_ADDR3 0x12
473 #define CORTINA_PHY_ADDR4 0x13
474 #define AQ_PHY_ADDR1 0x00
475 #define AQ_PHY_ADDR2 0x01
476 #define AQ_PHY_ADDR3 0x02
477 #define AQ_PHY_ADDR4 0x03
478 #define AQR405_IRQ_MASK 0x36
480 #include <asm/fsl_secure_boot.h>
482 #endif /* __LS2_RDB_H */