1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2019-2021 NXP
4 * Copyright 2015 Freescale Semiconductor
10 #include "ls2080a_common.h"
12 #define I2C_MUX_CH_VOL_MONITOR 0xa
13 #define I2C_VOL_MONITOR_ADDR 0x38
15 /* step the IR regulator in 5mV increments */
16 #define IR_VDD_STEP_DOWN 5
17 #define IR_VDD_STEP_UP 5
18 /* The lowest and highest voltage allowed for LS2080ARDB */
19 #define VDD_MV_MIN 819
20 #define VDD_MV_MAX 1212
22 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
24 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
25 #define SPD_EEPROM_ADDRESS1 0x51
26 #define SPD_EEPROM_ADDRESS2 0x52
27 #define SPD_EEPROM_ADDRESS3 0x53
28 #define SPD_EEPROM_ADDRESS4 0x54
29 #define SPD_EEPROM_ADDRESS5 0x55
30 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
31 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
33 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
35 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
36 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
37 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
39 #define CONFIG_SYS_NOR0_CSPR \
40 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
44 #define CONFIG_SYS_NOR0_CSPR_EARLY \
45 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
49 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
50 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
51 FTIM0_NOR_TEADC(0x5) | \
53 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
54 FTIM1_NOR_TRAD_NOR(0x1a) |\
55 FTIM1_NOR_TSEQRAD_NOR(0x13))
56 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
57 FTIM2_NOR_TCH(0x4) | \
58 FTIM2_NOR_TWPH(0x0E) | \
60 #define CONFIG_SYS_NOR_FTIM3 0x04000000
61 #define CONFIG_SYS_IFC_CCR 0x01000000
63 #ifdef CONFIG_MTD_NOR_FLASH
64 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
66 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
67 CONFIG_SYS_FLASH_BASE + 0x40000000}
70 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
71 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
73 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
74 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
75 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
76 | CSPR_MSEL_NAND /* MSEL = NAND */ \
78 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
80 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
81 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
82 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
83 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
84 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
85 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
86 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
88 /* ONFI NAND Flash mode0 Timing Params */
89 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
90 FTIM0_NAND_TWP(0x30) | \
91 FTIM0_NAND_TWCHT(0x0e) | \
93 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
94 FTIM1_NAND_TWBE(0xab) | \
95 FTIM1_NAND_TRR(0x1c) | \
97 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
98 FTIM2_NAND_TREH(0x14) | \
99 FTIM2_NAND_TWHRE(0x3c))
100 #define CONFIG_SYS_NAND_FTIM3 0x0
102 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
103 #define CONFIG_SYS_MAX_NAND_DEVICE 1
104 #define CONFIG_MTD_NAND_VERIFY_WRITE
106 #define QIXIS_LBMAP_SWITCH 0x06
107 #define QIXIS_LBMAP_MASK 0x0f
108 #define QIXIS_LBMAP_SHIFT 0
109 #define QIXIS_LBMAP_DFLTBANK 0x00
110 #define QIXIS_LBMAP_ALTBANK 0x04
111 #define QIXIS_LBMAP_NAND 0x09
112 #define QIXIS_RST_CTL_RESET 0x31
113 #define QIXIS_RST_CTL_RESET_EN 0x30
114 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
115 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
116 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
117 #define QIXIS_RCW_SRC_NAND 0x119
118 #define QIXIS_RST_FORCE_MEM 0x01
120 #define CONFIG_SYS_CSPR3_EXT (0x0)
121 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
125 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
130 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
131 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
132 /* QIXIS Timing parameters for IFC CS3 */
133 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
134 FTIM0_GPCM_TEADC(0x0e) | \
135 FTIM0_GPCM_TEAHC(0x0e))
136 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
137 FTIM1_GPCM_TRAD(0x3f))
138 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
139 FTIM2_GPCM_TCH(0xf) | \
140 FTIM2_GPCM_TWP(0x3E))
141 #define CONFIG_SYS_CS3_FTIM3 0x0
143 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
144 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
145 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
146 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
147 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
148 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
149 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
150 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
151 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
152 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
153 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
154 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
155 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
156 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
157 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
158 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
159 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
160 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
162 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
164 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
165 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
166 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
167 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
168 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
169 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
170 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
171 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
172 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
173 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
174 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
175 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
176 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
177 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
178 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
179 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
180 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
183 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
185 #ifdef CONFIG_TARGET_LS2081ARDB
186 #define QIXIS_QMAP_MASK 0x07
187 #define QIXIS_QMAP_SHIFT 5
188 #define QIXIS_LBMAP_DFLTBANK 0x00
189 #define QIXIS_LBMAP_QSPI 0x00
190 #define QIXIS_RCW_SRC_QSPI 0x62
191 #define QIXIS_LBMAP_ALTBANK 0x20
192 #define QIXIS_RST_CTL_RESET 0x31
193 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
194 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
195 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
196 #define QIXIS_LBMAP_MASK 0x0f
197 #define QIXIS_RST_CTL_RESET_EN 0x30
203 #ifdef CONFIG_TARGET_LS2081ARDB
204 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
206 #define I2C_MUX_PCA_ADDR 0x75
207 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
209 /* I2C bus multiplexer */
210 #define I2C_MUX_CH_DEFAULT 0x8
218 #ifdef CONFIG_TARGET_LS2081ARDB
219 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
221 #define CONFIG_RTC_DS3231 1
222 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
226 #define CONFIG_SYS_I2C_EEPROM_NXID
227 #define CONFIG_SYS_EEPROM_BUS_NUM 0
229 #define CONFIG_FSL_MEMAC
231 #define BOOT_TARGET_DEVICES(func) \
234 func(SCSI, scsi, 0) \
236 #include <config_distro_bootcmd.h>
238 #ifdef CONFIG_TFABOOT
239 #define QSPI_MC_INIT_CMD \
241 "sf read 0x80640000 0x640000 0x80000; " \
242 "env exists secureboot && " \
243 "esbc_validate 0x80640000 && " \
244 "esbc_validate 0x80680000; " \
245 "sf read 0x80a00000 0xa00000 0x200000; " \
246 "sf read 0x80e00000 0xe00000 0x100000; " \
247 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
248 #define SD_MC_INIT_CMD \
249 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
250 "mmc read 0x80e00000 0x7000 0x800;" \
251 "env exists secureboot && " \
252 "mmc read 0x80640000 0x3200 0x20 && " \
253 "mmc read 0x80680000 0x3400 0x20 && " \
254 "esbc_validate 0x80640000 && " \
255 "esbc_validate 0x80680000 ;" \
256 "fsl_mc start mc 0x80a00000 0x80e00000\0"
257 #define IFC_MC_INIT_CMD \
258 "env exists secureboot && " \
259 "esbc_validate 0x580640000 && " \
260 "esbc_validate 0x580680000; " \
261 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
263 #ifdef CONFIG_QSPI_BOOT
264 #define MC_INIT_CMD \
265 "mcinitcmd=sf probe 0:0; " \
266 "sf read 0x80640000 0x640000 0x80000; " \
267 "env exists secureboot && " \
268 "esbc_validate 0x80640000 && " \
269 "esbc_validate 0x80680000; " \
270 "sf read 0x80a00000 0xa00000 0x200000; " \
271 "sf read 0x80e00000 0xe00000 0x100000; " \
272 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
273 #elif defined(CONFIG_SD_BOOT)
274 #define MC_INIT_CMD \
275 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
276 "mmc read 0x80e00000 0x7000 0x800;" \
277 "env exists secureboot && " \
278 "mmc read 0x80640000 0x3200 0x20 && " \
279 "mmc read 0x80680000 0x3400 0x20 && " \
280 "esbc_validate 0x80640000 && " \
281 "esbc_validate 0x80680000 ;" \
282 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
283 "mcmemsize=0x70000000\0"
285 #define MC_INIT_CMD \
286 "mcinitcmd=env exists secureboot && " \
287 "esbc_validate 0x580640000 && " \
288 "esbc_validate 0x580680000; " \
289 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
293 /* Initial environment variables */
294 #undef CONFIG_EXTRA_ENV_SETTINGS
295 #ifdef CONFIG_TFABOOT
296 #define CONFIG_EXTRA_ENV_SETTINGS \
297 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
298 "ramdisk_addr=0x800000\0" \
299 "ramdisk_size=0x2000000\0" \
300 "fdt_high=0xa0000000\0" \
301 "initrd_high=0xffffffffffffffff\0" \
302 "kernel_addr=0x581000000\0" \
303 "kernel_start=0x1000000\0" \
304 "kernelheader_start=0x800000\0" \
305 "scriptaddr=0x80000000\0" \
306 "scripthdraddr=0x80080000\0" \
307 "fdtheader_addr_r=0x80100000\0" \
308 "kernelheader_addr_r=0x80200000\0" \
309 "kernelheader_addr=0x580600000\0" \
310 "kernel_addr_r=0x81000000\0" \
311 "kernelheader_size=0x40000\0" \
312 "fdt_addr_r=0x90000000\0" \
313 "load_addr=0xa0000000\0" \
314 "kernel_size=0x2800000\0" \
315 "kernel_addr_sd=0x8000\0" \
316 "kernel_size_sd=0x14000\0" \
317 "console=ttyAMA0,38400n8\0" \
318 "mcmemsize=0x70000000\0" \
319 "sd_bootcmd=echo Trying load from SD ..;" \
320 "mmcinfo; mmc read $load_addr " \
321 "$kernel_addr_sd $kernel_size_sd && " \
322 "bootm $load_addr#$board\0" \
325 "boot_scripts=ls2088ardb_boot.scr\0" \
326 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
327 "scan_dev_for_boot_part=" \
328 "part list ${devtype} ${devnum} devplist; " \
329 "env exists devplist || setenv devplist 1; " \
330 "for distro_bootpart in ${devplist}; do " \
331 "if fstype ${devtype} " \
332 "${devnum}:${distro_bootpart} " \
333 "bootfstype; then " \
334 "run scan_dev_for_boot; " \
338 "load ${devtype} ${devnum}:${distro_bootpart} " \
339 "${scriptaddr} ${prefix}${script}; " \
340 "env exists secureboot && load ${devtype} " \
341 "${devnum}:${distro_bootpart} " \
342 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
343 "&& esbc_validate ${scripthdraddr};" \
344 "source ${scriptaddr}\0" \
345 "qspi_bootcmd=echo Trying load from qspi..;" \
346 "sf probe && sf read $load_addr " \
347 "$kernel_start $kernel_size ; env exists secureboot &&" \
348 "sf read $kernelheader_addr_r $kernelheader_start " \
349 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
350 " bootm $load_addr#$board\0" \
351 "nor_bootcmd=echo Trying load from nor..;" \
352 "cp.b $kernel_addr $load_addr " \
353 "$kernel_size ; env exists secureboot && " \
354 "cp.b $kernelheader_addr $kernelheader_addr_r " \
355 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
356 "bootm $load_addr#$board\0"
358 #define CONFIG_EXTRA_ENV_SETTINGS \
359 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
360 "ramdisk_addr=0x800000\0" \
361 "ramdisk_size=0x2000000\0" \
362 "fdt_high=0xa0000000\0" \
363 "initrd_high=0xffffffffffffffff\0" \
364 "kernel_addr=0x581000000\0" \
365 "kernel_start=0x1000000\0" \
366 "kernelheader_start=0x600000\0" \
367 "scriptaddr=0x80000000\0" \
368 "scripthdraddr=0x80080000\0" \
369 "fdtheader_addr_r=0x80100000\0" \
370 "kernelheader_addr_r=0x80200000\0" \
371 "kernelheader_addr=0x580600000\0" \
372 "kernel_addr_r=0x81000000\0" \
373 "kernelheader_size=0x40000\0" \
374 "fdt_addr_r=0x90000000\0" \
375 "load_addr=0xa0000000\0" \
376 "kernel_size=0x2800000\0" \
377 "kernel_addr_sd=0x8000\0" \
378 "kernel_size_sd=0x14000\0" \
379 "console=ttyAMA0,38400n8\0" \
380 "mcmemsize=0x70000000\0" \
381 "sd_bootcmd=echo Trying load from SD ..;" \
382 "mmcinfo; mmc read $load_addr " \
383 "$kernel_addr_sd $kernel_size_sd && " \
384 "bootm $load_addr#$board\0" \
387 "boot_scripts=ls2088ardb_boot.scr\0" \
388 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
389 "scan_dev_for_boot_part=" \
390 "part list ${devtype} ${devnum} devplist; " \
391 "env exists devplist || setenv devplist 1; " \
392 "for distro_bootpart in ${devplist}; do " \
393 "if fstype ${devtype} " \
394 "${devnum}:${distro_bootpart} " \
395 "bootfstype; then " \
396 "run scan_dev_for_boot; " \
400 "load ${devtype} ${devnum}:${distro_bootpart} " \
401 "${scriptaddr} ${prefix}${script}; " \
402 "env exists secureboot && load ${devtype} " \
403 "${devnum}:${distro_bootpart} " \
404 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
405 "env exists secureboot " \
406 "&& esbc_validate ${scripthdraddr};" \
407 "source ${scriptaddr}\0" \
408 "qspi_bootcmd=echo Trying load from qspi..;" \
409 "sf probe && sf read $load_addr " \
410 "$kernel_start $kernel_size ; env exists secureboot &&" \
411 "sf read $kernelheader_addr_r $kernelheader_start " \
412 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
413 " bootm $load_addr#$board\0" \
414 "nor_bootcmd=echo Trying load from nor..;" \
415 "cp.b $kernel_addr $load_addr " \
416 "$kernel_size ; env exists secureboot && " \
417 "cp.b $kernelheader_addr $kernelheader_addr_r " \
418 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
419 "bootm $load_addr#$board\0"
422 #ifdef CONFIG_TFABOOT
423 #define QSPI_NOR_BOOTCOMMAND \
425 "sf read 0x806c0000 0x6c0000 0x40000; " \
426 "env exists mcinitcmd && env exists secureboot "\
427 "&& esbc_validate 0x806c0000; " \
428 "sf read 0x80d00000 0xd00000 0x100000; " \
429 "env exists mcinitcmd && " \
430 "fsl_mc lazyapply dpl 0x80d00000; " \
431 "run distro_bootcmd;run qspi_bootcmd; " \
432 "env exists secureboot && esbc_halt;"
434 /* Try to boot an on-SD kernel first, then do normal distro boot */
435 #define SD_BOOTCOMMAND \
436 "env exists mcinitcmd && env exists secureboot "\
437 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
438 "&& esbc_validate $load_addr; " \
439 "env exists mcinitcmd && run mcinitcmd " \
440 "&& mmc read 0x80d00000 0x6800 0x800 " \
441 "&& fsl_mc lazyapply dpl 0x80d00000; " \
442 "run distro_bootcmd;run sd_bootcmd; " \
443 "env exists secureboot && esbc_halt;"
445 /* Try to boot an on-NOR kernel first, then do normal distro boot */
446 #define IFC_NOR_BOOTCOMMAND \
447 "env exists mcinitcmd && env exists secureboot "\
448 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
449 "&& fsl_mc lazyapply dpl 0x580d00000;" \
450 "run distro_bootcmd;run nor_bootcmd; " \
451 "env exists secureboot && esbc_halt;"
453 #ifdef CONFIG_QSPI_BOOT
454 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
455 #elif defined(CONFIG_SD_BOOT)
456 /* Try to boot an on-SD kernel first, then do normal distro boot */
458 /* Try to boot an on-NOR kernel first, then do normal distro boot */
462 /* MAC/PHY configuration */
463 #define CORTINA_PHY_ADDR1 0x10
464 #define CORTINA_PHY_ADDR2 0x11
465 #define CORTINA_PHY_ADDR3 0x12
466 #define CORTINA_PHY_ADDR4 0x13
467 #define AQ_PHY_ADDR1 0x00
468 #define AQ_PHY_ADDR2 0x01
469 #define AQ_PHY_ADDR3 0x02
470 #define AQ_PHY_ADDR4 0x03
471 #define AQR405_IRQ_MASK 0x36
473 #include <asm/fsl_secure_boot.h>
475 #endif /* __LS2_RDB_H */