include/configs/ls2080ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2021 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_RDB_H
   8 #define __LS2_RDB_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #define I2C_MUX_CH_VOL_MONITOR          0xa
  13 #define I2C_VOL_MONITOR_ADDR            0x38
  14
  15 /* step the IR regulator in 5mV increments */
  16 #define IR_VDD_STEP_DOWN                5
  17 #define IR_VDD_STEP_UP                  5
  18 /* The lowest and highest voltage allowed for LS2080ARDB */
  19 #define VDD_MV_MIN                      819
  20 #define VDD_MV_MAX                      1212
  21
  22 #define COUNTER_FREQUENCY_REAL          (get_board_sys_clk()/4)
  23
  24 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  25 #define SPD_EEPROM_ADDRESS1     0x51
  26 #define SPD_EEPROM_ADDRESS2     0x52
  27 #define SPD_EEPROM_ADDRESS3     0x53
  28 #define SPD_EEPROM_ADDRESS4     0x54
  29 #define SPD_EEPROM_ADDRESS5     0x55
  30 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  31 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  32 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  33 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  34 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  35 #endif
  36
  37 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
  38
  39 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  40 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  41 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  42
  43 #define CONFIG_SYS_NOR0_CSPR                                    \
  44         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  45         CSPR_PORT_SIZE_16                                       | \
  46         CSPR_MSEL_NOR                                           | \
  47         CSPR_V)
  48 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  49         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  50         CSPR_PORT_SIZE_16                                       | \
  51         CSPR_MSEL_NOR                                           | \
  52         CSPR_V)
  53 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  54 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  55                                 FTIM0_NOR_TEADC(0x5) | \
  56                                 FTIM0_NOR_TEAHC(0x5))
  57 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  58                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  59                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  60 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  61                                 FTIM2_NOR_TCH(0x4) | \
  62                                 FTIM2_NOR_TWPH(0x0E) | \
  63                                 FTIM2_NOR_TWP(0x1c))
  64 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  65 #define CONFIG_SYS_IFC_CCR      0x01000000
  66
  67 #ifdef CONFIG_MTD_NOR_FLASH
  68 #define CONFIG_SYS_FLASH_QUIET_TEST
  69 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  70
  71 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  72 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  73 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  74
  75 #define CONFIG_SYS_FLASH_EMPTY_INFO
  76 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  77                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  78 #endif
  79
  80 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  81 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  82
  83 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  84 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  85                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  86                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  87                                 | CSPR_V)
  88 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  89
  90 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  91                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  92                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  93                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  94                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
  95                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
  96                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
  97
  98 /* ONFI NAND Flash mode0 Timing Params */
  99 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
 100                                         FTIM0_NAND_TWP(0x30)   | \
 101                                         FTIM0_NAND_TWCHT(0x0e) | \
 102                                         FTIM0_NAND_TWH(0x14))
 103 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
 104                                         FTIM1_NAND_TWBE(0xab)  | \
 105                                         FTIM1_NAND_TRR(0x1c)   | \
 106                                         FTIM1_NAND_TRP(0x30))
 107 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
 108                                         FTIM2_NAND_TREH(0x14) | \
 109                                         FTIM2_NAND_TWHRE(0x3c))
 110 #define CONFIG_SYS_NAND_FTIM3           0x0
 111
 112 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 113 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 114 #define CONFIG_MTD_NAND_VERIFY_WRITE
 115
 116 #define QIXIS_LBMAP_SWITCH              0x06
 117 #define QIXIS_LBMAP_MASK                0x0f
 118 #define QIXIS_LBMAP_SHIFT               0
 119 #define QIXIS_LBMAP_DFLTBANK            0x00
 120 #define QIXIS_LBMAP_ALTBANK             0x04
 121 #define QIXIS_LBMAP_NAND                0x09
 122 #define QIXIS_RST_CTL_RESET             0x31
 123 #define QIXIS_RST_CTL_RESET_EN          0x30
 124 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 125 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 126 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 127 #define QIXIS_RCW_SRC_NAND              0x119
 128 #define QIXIS_RST_FORCE_MEM             0x01
 129
 130 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 131 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 132                                 | CSPR_PORT_SIZE_8 \
 133                                 | CSPR_MSEL_GPCM \
 134                                 | CSPR_V)
 135 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 136                                 | CSPR_PORT_SIZE_8 \
 137                                 | CSPR_MSEL_GPCM \
 138                                 | CSPR_V)
 139
 140 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 141 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 142 /* QIXIS Timing parameters for IFC CS3 */
 143 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 144                                         FTIM0_GPCM_TEADC(0x0e) | \
 145                                         FTIM0_GPCM_TEAHC(0x0e))
 146 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 147                                         FTIM1_GPCM_TRAD(0x3f))
 148 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 149                                         FTIM2_GPCM_TCH(0xf) | \
 150                                         FTIM2_GPCM_TWP(0x3E))
 151 #define CONFIG_SYS_CS3_FTIM3            0x0
 152
 153 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
 154 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 155 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
 156 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
 157 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 158 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 159 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 160 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 161 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 162 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 163 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 164 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 165 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 166 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 167 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 168 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 169 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 170 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 171
 172 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
 173 #else
 174 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 175 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 176 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 177 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 178 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 179 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 180 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 181 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 182 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 183 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 184 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 185 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 186 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 187 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 188 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 189 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 190 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 191 #endif
 192
 193 /* Debug Server firmware */
 194 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 195 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 196 #endif
 197 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 198
 199 #ifdef CONFIG_TARGET_LS2081ARDB
 200 #define QIXIS_QMAP_MASK                 0x07
 201 #define QIXIS_QMAP_SHIFT                5
 202 #define QIXIS_LBMAP_DFLTBANK            0x00
 203 #define QIXIS_LBMAP_QSPI                0x00
 204 #define QIXIS_RCW_SRC_QSPI              0x62
 205 #define QIXIS_LBMAP_ALTBANK             0x20
 206 #define QIXIS_RST_CTL_RESET             0x31
 207 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 208 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 209 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 210 #define QIXIS_LBMAP_MASK                0x0f
 211 #define QIXIS_RST_CTL_RESET_EN          0x30
 212 #endif
 213
 214 /*
 215  * I2C
 216  */
 217 #ifdef CONFIG_TARGET_LS2081ARDB
 218 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 219 #endif
 220 #define I2C_MUX_PCA_ADDR                0x75
 221 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
 222
 223 /* I2C bus multiplexer */
 224 #define I2C_MUX_CH_DEFAULT      0x8
 225
 226 /* SPI */
 227
 228 /*
 229  * RTC configuration
 230  */
 231 #define RTC
 232 #ifdef CONFIG_TARGET_LS2081ARDB
 233 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 234 #else
 235 #define CONFIG_RTC_DS3231               1
 236 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 237 #endif
 238
 239 /* EEPROM */
 240 #define CONFIG_SYS_I2C_EEPROM_NXID
 241 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 242
 243 #define CONFIG_FSL_MEMAC
 244
 245 #ifdef CONFIG_PCI
 246 #define CONFIG_PCI_SCAN_SHOW
 247 #endif
 248
 249 #define BOOT_TARGET_DEVICES(func) \
 250         func(USB, usb, 0) \
 251         func(MMC, mmc, 0) \
 252         func(SCSI, scsi, 0) \
 253         func(DHCP, dhcp, na)
 254 #include <config_distro_bootcmd.h>
 255
 256 #ifdef CONFIG_TFABOOT
 257 #define QSPI_MC_INIT_CMD                                \
 258         "sf probe 0:0; "                                \
 259         "sf read 0x80640000 0x640000 0x80000; "         \
 260         "env exists secureboot && "                     \
 261         "esbc_validate 0x80640000 && "                  \
 262         "esbc_validate 0x80680000; "                    \
 263         "sf read 0x80a00000 0xa00000 0x200000; "        \
 264         "sf read 0x80e00000 0xe00000 0x100000; "        \
 265         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 266 #define SD_MC_INIT_CMD                          \
 267         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 268         "mmc read 0x80e00000 0x7000 0x800;"     \
 269         "env exists secureboot && "             \
 270         "mmc read 0x80640000 0x3200 0x20 && "   \
 271         "mmc read 0x80680000 0x3400 0x20 && "   \
 272         "esbc_validate 0x80640000 && "          \
 273         "esbc_validate 0x80680000 ;"            \
 274         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 275 #define IFC_MC_INIT_CMD                         \
 276         "env exists secureboot && "     \
 277         "esbc_validate 0x580640000 && "         \
 278         "esbc_validate 0x580680000; "           \
 279         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 280 #else
 281 #ifdef CONFIG_QSPI_BOOT
 282 #define MC_INIT_CMD                                     \
 283         "mcinitcmd=sf probe 0:0; "                      \
 284         "sf read 0x80640000 0x640000 0x80000; "         \
 285         "env exists secureboot && "                     \
 286         "esbc_validate 0x80640000 && "                  \
 287         "esbc_validate 0x80680000; "                    \
 288         "sf read 0x80a00000 0xa00000 0x200000; "        \
 289         "sf read 0x80e00000 0xe00000 0x100000; "        \
 290         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 291 #elif defined(CONFIG_SD_BOOT)
 292 #define MC_INIT_CMD                             \
 293         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 294         "mmc read 0x80e00000 0x7000 0x800;"     \
 295         "env exists secureboot && "             \
 296         "mmc read 0x80640000 0x3200 0x20 && "   \
 297         "mmc read 0x80680000 0x3400 0x20 && "   \
 298         "esbc_validate 0x80640000 && "          \
 299         "esbc_validate 0x80680000 ;"            \
 300         "fsl_mc start mc 0x80a00000 0x80e00000\0" \
 301         "mcmemsize=0x70000000\0"
 302 #else
 303 #define MC_INIT_CMD                             \
 304         "mcinitcmd=env exists secureboot && "   \
 305         "esbc_validate 0x580640000 && "         \
 306         "esbc_validate 0x580680000; "           \
 307         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 308 #endif
 309 #endif
 310
 311 /* Initial environment variables */
 312 #undef CONFIG_EXTRA_ENV_SETTINGS
 313 #ifdef CONFIG_TFABOOT
 314 #define CONFIG_EXTRA_ENV_SETTINGS               \
 315         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 316         "ramdisk_addr=0x800000\0"               \
 317         "ramdisk_size=0x2000000\0"              \
 318         "fdt_high=0xa0000000\0"                 \
 319         "initrd_high=0xffffffffffffffff\0"      \
 320         "kernel_addr=0x581000000\0"             \
 321         "kernel_start=0x1000000\0"              \
 322         "kernelheader_start=0x800000\0"         \
 323         "scriptaddr=0x80000000\0"               \
 324         "scripthdraddr=0x80080000\0"            \
 325         "fdtheader_addr_r=0x80100000\0"         \
 326         "kernelheader_addr_r=0x80200000\0"      \
 327         "kernelheader_addr=0x580600000\0"       \
 328         "kernel_addr_r=0x81000000\0"            \
 329         "kernelheader_size=0x40000\0"           \
 330         "fdt_addr_r=0x90000000\0"               \
 331         "load_addr=0xa0000000\0"                \
 332         "kernel_size=0x2800000\0"               \
 333         "kernel_addr_sd=0x8000\0"               \
 334         "kernel_size_sd=0x14000\0"              \
 335         "console=ttyAMA0,38400n8\0"             \
 336         "mcmemsize=0x70000000\0"                \
 337         "sd_bootcmd=echo Trying load from SD ..;" \
 338         "mmcinfo; mmc read $load_addr "         \
 339         "$kernel_addr_sd $kernel_size_sd && "   \
 340         "bootm $load_addr#$board\0"             \
 341         QSPI_MC_INIT_CMD                                \
 342         BOOTENV                                 \
 343         "boot_scripts=ls2088ardb_boot.scr\0"    \
 344         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 345         "scan_dev_for_boot_part="               \
 346                 "part list ${devtype} ${devnum} devplist; "     \
 347                 "env exists devplist || setenv devplist 1; "    \
 348                 "for distro_bootpart in ${devplist}; do "       \
 349                         "if fstype ${devtype} "                 \
 350                                 "${devnum}:${distro_bootpart} " \
 351                                 "bootfstype; then "             \
 352                                 "run scan_dev_for_boot; "       \
 353                         "fi; "                                  \
 354                 "done\0"                                        \
 355         "boot_a_script="                                        \
 356                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 357                         "${scriptaddr} ${prefix}${script}; "    \
 358                 "env exists secureboot && load ${devtype} "     \
 359                         "${devnum}:${distro_bootpart} "         \
 360                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 361                         "&& esbc_validate ${scripthdraddr};"    \
 362                 "source ${scriptaddr}\0"                        \
 363         "qspi_bootcmd=echo Trying load from qspi..;"            \
 364                 "sf probe && sf read $load_addr "               \
 365                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 366                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 367                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 368                 " bootm $load_addr#$board\0"                    \
 369         "nor_bootcmd=echo Trying load from nor..;"              \
 370                 "cp.b $kernel_addr $load_addr "                 \
 371                 "$kernel_size ; env exists secureboot && "      \
 372                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 373                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 374                 "bootm $load_addr#$board\0"
 375 #else
 376 #define CONFIG_EXTRA_ENV_SETTINGS               \
 377         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 378         "ramdisk_addr=0x800000\0"               \
 379         "ramdisk_size=0x2000000\0"              \
 380         "fdt_high=0xa0000000\0"                 \
 381         "initrd_high=0xffffffffffffffff\0"      \
 382         "kernel_addr=0x581000000\0"             \
 383         "kernel_start=0x1000000\0"              \
 384         "kernelheader_start=0x600000\0"         \
 385         "scriptaddr=0x80000000\0"               \
 386         "scripthdraddr=0x80080000\0"            \
 387         "fdtheader_addr_r=0x80100000\0"         \
 388         "kernelheader_addr_r=0x80200000\0"      \
 389         "kernelheader_addr=0x580600000\0"       \
 390         "kernel_addr_r=0x81000000\0"            \
 391         "kernelheader_size=0x40000\0"           \
 392         "fdt_addr_r=0x90000000\0"               \
 393         "load_addr=0xa0000000\0"                \
 394         "kernel_size=0x2800000\0"               \
 395         "kernel_addr_sd=0x8000\0"               \
 396         "kernel_size_sd=0x14000\0"              \
 397         "console=ttyAMA0,38400n8\0"             \
 398         "mcmemsize=0x70000000\0"                \
 399         "sd_bootcmd=echo Trying load from SD ..;" \
 400         "mmcinfo; mmc read $load_addr "         \
 401         "$kernel_addr_sd $kernel_size_sd && "   \
 402         "bootm $load_addr#$board\0"             \
 403         MC_INIT_CMD                             \
 404         BOOTENV                                 \
 405         "boot_scripts=ls2088ardb_boot.scr\0"    \
 406         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 407         "scan_dev_for_boot_part="               \
 408                 "part list ${devtype} ${devnum} devplist; "     \
 409                 "env exists devplist || setenv devplist 1; "    \
 410                 "for distro_bootpart in ${devplist}; do "       \
 411                         "if fstype ${devtype} "                 \
 412                                 "${devnum}:${distro_bootpart} " \
 413                                 "bootfstype; then "             \
 414                                 "run scan_dev_for_boot; "       \
 415                         "fi; "                                  \
 416                 "done\0"                                        \
 417         "boot_a_script="                                        \
 418                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 419                         "${scriptaddr} ${prefix}${script}; "    \
 420                 "env exists secureboot && load ${devtype} "     \
 421                         "${devnum}:${distro_bootpart} "         \
 422                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 423                         "env exists secureboot "        \
 424                         "&& esbc_validate ${scripthdraddr};"    \
 425                 "source ${scriptaddr}\0"                        \
 426         "qspi_bootcmd=echo Trying load from qspi..;"            \
 427                 "sf probe && sf read $load_addr "               \
 428                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 429                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 430                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 431                 " bootm $load_addr#$board\0"                    \
 432         "nor_bootcmd=echo Trying load from nor..;"              \
 433                 "cp.b $kernel_addr $load_addr "                 \
 434                 "$kernel_size ; env exists secureboot && "      \
 435                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 436                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 437                 "bootm $load_addr#$board\0"
 438 #endif
 439
 440 #ifdef CONFIG_TFABOOT
 441 #define QSPI_NOR_BOOTCOMMAND                                            \
 442                         "sf probe 0:0; "                                \
 443                         "sf read 0x806c0000 0x6c0000 0x40000; "         \
 444                         "env exists mcinitcmd && env exists secureboot "\
 445                         "&& esbc_validate 0x806c0000; "                 \
 446                         "sf read 0x80d00000 0xd00000 0x100000; "        \
 447                         "env exists mcinitcmd && "                      \
 448                         "fsl_mc lazyapply dpl 0x80d00000; "             \
 449                         "run distro_bootcmd;run qspi_bootcmd; "         \
 450                         "env exists secureboot && esbc_halt;"
 451
 452 /* Try to boot an on-SD kernel first, then do normal distro boot */
 453 #define SD_BOOTCOMMAND                                          \
 454                         "env exists mcinitcmd && env exists secureboot "\
 455                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 456                         "&& esbc_validate $load_addr; "                 \
 457                         "env exists mcinitcmd && run mcinitcmd "        \
 458                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 459                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 460                         "run distro_bootcmd;run sd_bootcmd; "           \
 461                         "env exists secureboot && esbc_halt;"
 462
 463 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 464 #define IFC_NOR_BOOTCOMMAND                                             \
 465                         "env exists mcinitcmd && env exists secureboot "\
 466                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 467                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 468                         "run distro_bootcmd;run nor_bootcmd; "          \
 469                         "env exists secureboot && esbc_halt;"
 470 #else
 471 #ifdef CONFIG_QSPI_BOOT
 472 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 473 #elif defined(CONFIG_SD_BOOT)
 474 /* Try to boot an on-SD kernel first, then do normal distro boot */
 475 #else
 476 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 477 #endif
 478 #endif
 479
 480 /* MAC/PHY configuration */
 481 #define CORTINA_PHY_ADDR1       0x10
 482 #define CORTINA_PHY_ADDR2       0x11
 483 #define CORTINA_PHY_ADDR3       0x12
 484 #define CORTINA_PHY_ADDR4       0x13
 485 #define AQ_PHY_ADDR1            0x00
 486 #define AQ_PHY_ADDR2            0x01
 487 #define AQ_PHY_ADDR3            0x02
 488 #define AQ_PHY_ADDR4            0x03
 489 #define AQR405_IRQ_MASK         0x36
 490
 491 #include <asm/fsl_secure_boot.h>
 492
 493 #endif /* __LS2_RDB_H */