include/configs/ls2080ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2021 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_RDB_H
   8 #define __LS2_RDB_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #ifdef CONFIG_FSL_QSPI
  13 #ifdef CONFIG_TARGET_LS2081ARDB
  14 #define CONFIG_QIXIS_I2C_ACCESS
  15 #endif
  16 #endif
  17
  18 #define I2C_MUX_CH_VOL_MONITOR          0xa
  19 #define I2C_VOL_MONITOR_ADDR            0x38
  20 #define CONFIG_VOL_MONITOR_IR36021_READ
  21 #define CONFIG_VOL_MONITOR_IR36021_SET
  22
  23 #define CONFIG_VID_FLS_ENV              "ls2080ardb_vdd_mv"
  24 #ifndef CONFIG_SPL_BUILD
  25 #define CONFIG_VID
  26 #endif
  27 /* step the IR regulator in 5mV increments */
  28 #define IR_VDD_STEP_DOWN                5
  29 #define IR_VDD_STEP_UP                  5
  30 /* The lowest and highest voltage allowed for LS2080ARDB */
  31 #define VDD_MV_MIN                      819
  32 #define VDD_MV_MAX                      1212
  33
  34 #ifndef __ASSEMBLY__
  35 unsigned long get_board_sys_clk(void);
  36 #endif
  37
  38 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  39 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  40
  41 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  42 #define SPD_EEPROM_ADDRESS1     0x51
  43 #define SPD_EEPROM_ADDRESS2     0x52
  44 #define SPD_EEPROM_ADDRESS3     0x53
  45 #define SPD_EEPROM_ADDRESS4     0x54
  46 #define SPD_EEPROM_ADDRESS5     0x55
  47 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  48 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  49 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  50 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  51 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  52 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  53 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  54 #endif
  55
  56 /* SATA */
  57 #define CONFIG_SCSI_AHCI_PLAT
  58
  59 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  60 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  61
  62 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  63 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  64 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  65                                                 CONFIG_SYS_SCSI_MAX_LUN)
  66
  67 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
  68
  69 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  70 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  71 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  72
  73 #define CONFIG_SYS_NOR0_CSPR                                    \
  74         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  75         CSPR_PORT_SIZE_16                                       | \
  76         CSPR_MSEL_NOR                                           | \
  77         CSPR_V)
  78 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  79         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  80         CSPR_PORT_SIZE_16                                       | \
  81         CSPR_MSEL_NOR                                           | \
  82         CSPR_V)
  83 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  84 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  85                                 FTIM0_NOR_TEADC(0x5) | \
  86                                 FTIM0_NOR_TEAHC(0x5))
  87 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  88                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  89                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  90 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  91                                 FTIM2_NOR_TCH(0x4) | \
  92                                 FTIM2_NOR_TWPH(0x0E) | \
  93                                 FTIM2_NOR_TWP(0x1c))
  94 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  95 #define CONFIG_SYS_IFC_CCR      0x01000000
  96
  97 #ifdef CONFIG_MTD_NOR_FLASH
  98 #define CONFIG_SYS_FLASH_QUIET_TEST
  99 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 100
 101 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 102 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 103 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 104 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 105
 106 #define CONFIG_SYS_FLASH_EMPTY_INFO
 107 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
 108                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
 109 #endif
 110
 111 #define CONFIG_NAND_FSL_IFC
 112 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 113 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 114
 115 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 116 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 117                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 118                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 119                                 | CSPR_V)
 120 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 121
 122 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 123                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 124                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 125                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 126                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 127                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 128                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
 129
 130 #define CONFIG_SYS_NAND_ONFI_DETECTION
 131
 132 /* ONFI NAND Flash mode0 Timing Params */
 133 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
 134                                         FTIM0_NAND_TWP(0x30)   | \
 135                                         FTIM0_NAND_TWCHT(0x0e) | \
 136                                         FTIM0_NAND_TWH(0x14))
 137 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
 138                                         FTIM1_NAND_TWBE(0xab)  | \
 139                                         FTIM1_NAND_TRR(0x1c)   | \
 140                                         FTIM1_NAND_TRP(0x30))
 141 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
 142                                         FTIM2_NAND_TREH(0x14) | \
 143                                         FTIM2_NAND_TWHRE(0x3c))
 144 #define CONFIG_SYS_NAND_FTIM3           0x0
 145
 146 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 147 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 148 #define CONFIG_MTD_NAND_VERIFY_WRITE
 149
 150 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 151 #define QIXIS_LBMAP_SWITCH              0x06
 152 #define QIXIS_LBMAP_MASK                0x0f
 153 #define QIXIS_LBMAP_SHIFT               0
 154 #define QIXIS_LBMAP_DFLTBANK            0x00
 155 #define QIXIS_LBMAP_ALTBANK             0x04
 156 #define QIXIS_LBMAP_NAND                0x09
 157 #define QIXIS_RST_CTL_RESET             0x31
 158 #define QIXIS_RST_CTL_RESET_EN          0x30
 159 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 160 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 161 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 162 #define QIXIS_RCW_SRC_NAND              0x119
 163 #define QIXIS_RST_FORCE_MEM             0x01
 164
 165 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 166 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 167                                 | CSPR_PORT_SIZE_8 \
 168                                 | CSPR_MSEL_GPCM \
 169                                 | CSPR_V)
 170 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 171                                 | CSPR_PORT_SIZE_8 \
 172                                 | CSPR_MSEL_GPCM \
 173                                 | CSPR_V)
 174
 175 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 176 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 177 /* QIXIS Timing parameters for IFC CS3 */
 178 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 179                                         FTIM0_GPCM_TEADC(0x0e) | \
 180                                         FTIM0_GPCM_TEAHC(0x0e))
 181 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 182                                         FTIM1_GPCM_TRAD(0x3f))
 183 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 184                                         FTIM2_GPCM_TCH(0xf) | \
 185                                         FTIM2_GPCM_TWP(0x3E))
 186 #define CONFIG_SYS_CS3_FTIM3            0x0
 187
 188 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
 189 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 190 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
 191 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
 192 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 193 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 194 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 195 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 196 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 197 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 198 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 199 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 200 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 201 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 202 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 203 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 204 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 205 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 206
 207 #define CONFIG_SPL_PAD_TO               0x80000
 208 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (1024 * 1024)
 209 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
 210 #else
 211 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 212 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 213 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 214 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 215 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 216 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 217 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 218 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 219 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 220 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 221 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 222 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 223 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 224 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 225 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 226 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 227 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 228 #endif
 229
 230 /* Debug Server firmware */
 231 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 232 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 233 #endif
 234 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 235
 236 #ifdef CONFIG_TARGET_LS2081ARDB
 237 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 238 #define QIXIS_QMAP_MASK                 0x07
 239 #define QIXIS_QMAP_SHIFT                5
 240 #define QIXIS_LBMAP_DFLTBANK            0x00
 241 #define QIXIS_LBMAP_QSPI                0x00
 242 #define QIXIS_RCW_SRC_QSPI              0x62
 243 #define QIXIS_LBMAP_ALTBANK             0x20
 244 #define QIXIS_RST_CTL_RESET             0x31
 245 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 246 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 247 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 248 #define QIXIS_LBMAP_MASK                0x0f
 249 #define QIXIS_RST_CTL_RESET_EN          0x30
 250 #endif
 251
 252 /*
 253  * I2C
 254  */
 255 #ifdef CONFIG_TARGET_LS2081ARDB
 256 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 257 #endif
 258 #define I2C_MUX_PCA_ADDR                0x75
 259 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
 260
 261 /* I2C bus multiplexer */
 262 #define I2C_MUX_CH_DEFAULT      0x8
 263
 264 /* SPI */
 265 #if defined(CONFIG_FSL_DSPI)
 266 #define CONFIG_SPI_FLASH_STMICRO
 267 #endif
 268
 269 /*
 270  * RTC configuration
 271  */
 272 #define RTC
 273 #ifdef CONFIG_TARGET_LS2081ARDB
 274 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 275 #else
 276 #define CONFIG_RTC_DS3231               1
 277 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 278 #endif
 279
 280 /* EEPROM */
 281 #define CONFIG_SYS_I2C_EEPROM_NXID
 282 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 283
 284 #define CONFIG_FSL_MEMAC
 285
 286 #ifdef CONFIG_PCI
 287 #define CONFIG_PCI_SCAN_SHOW
 288 #endif
 289
 290 #define BOOT_TARGET_DEVICES(func) \
 291         func(USB, usb, 0) \
 292         func(MMC, mmc, 0) \
 293         func(SCSI, scsi, 0) \
 294         func(DHCP, dhcp, na)
 295 #include <config_distro_bootcmd.h>
 296
 297 #ifdef CONFIG_TFABOOT
 298 #define QSPI_MC_INIT_CMD                                \
 299         "sf probe 0:0; "                                \
 300         "sf read 0x80640000 0x640000 0x80000; "         \
 301         "env exists secureboot && "                     \
 302         "esbc_validate 0x80640000 && "                  \
 303         "esbc_validate 0x80680000; "                    \
 304         "sf read 0x80a00000 0xa00000 0x200000; "        \
 305         "sf read 0x80e00000 0xe00000 0x100000; "        \
 306         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 307 #define SD_MC_INIT_CMD                          \
 308         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 309         "mmc read 0x80e00000 0x7000 0x800;"     \
 310         "env exists secureboot && "             \
 311         "mmc read 0x80640000 0x3200 0x20 && "   \
 312         "mmc read 0x80680000 0x3400 0x20 && "   \
 313         "esbc_validate 0x80640000 && "          \
 314         "esbc_validate 0x80680000 ;"            \
 315         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 316 #define IFC_MC_INIT_CMD                         \
 317         "env exists secureboot && "     \
 318         "esbc_validate 0x580640000 && "         \
 319         "esbc_validate 0x580680000; "           \
 320         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 321 #else
 322 #ifdef CONFIG_QSPI_BOOT
 323 #define MC_INIT_CMD                                     \
 324         "mcinitcmd=sf probe 0:0; "                      \
 325         "sf read 0x80640000 0x640000 0x80000; "         \
 326         "env exists secureboot && "                     \
 327         "esbc_validate 0x80640000 && "                  \
 328         "esbc_validate 0x80680000; "                    \
 329         "sf read 0x80a00000 0xa00000 0x200000; "        \
 330         "sf read 0x80e00000 0xe00000 0x100000; "        \
 331         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 332 #elif defined(CONFIG_SD_BOOT)
 333 #define MC_INIT_CMD                             \
 334         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 335         "mmc read 0x80e00000 0x7000 0x800;"     \
 336         "env exists secureboot && "             \
 337         "mmc read 0x80640000 0x3200 0x20 && "   \
 338         "mmc read 0x80680000 0x3400 0x20 && "   \
 339         "esbc_validate 0x80640000 && "          \
 340         "esbc_validate 0x80680000 ;"            \
 341         "fsl_mc start mc 0x80a00000 0x80e00000\0" \
 342         "mcmemsize=0x70000000\0"
 343 #else
 344 #define MC_INIT_CMD                             \
 345         "mcinitcmd=env exists secureboot && "   \
 346         "esbc_validate 0x580640000 && "         \
 347         "esbc_validate 0x580680000; "           \
 348         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 349 #endif
 350 #endif
 351
 352 /* Initial environment variables */
 353 #undef CONFIG_EXTRA_ENV_SETTINGS
 354 #ifdef CONFIG_TFABOOT
 355 #define CONFIG_EXTRA_ENV_SETTINGS               \
 356         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 357         "ramdisk_addr=0x800000\0"               \
 358         "ramdisk_size=0x2000000\0"              \
 359         "fdt_high=0xa0000000\0"                 \
 360         "initrd_high=0xffffffffffffffff\0"      \
 361         "fdt_addr=0x64f00000\0"                 \
 362         "kernel_addr=0x581000000\0"             \
 363         "kernel_start=0x1000000\0"              \
 364         "kernelheader_start=0x800000\0"         \
 365         "scriptaddr=0x80000000\0"               \
 366         "scripthdraddr=0x80080000\0"            \
 367         "fdtheader_addr_r=0x80100000\0"         \
 368         "kernelheader_addr_r=0x80200000\0"      \
 369         "kernelheader_addr=0x580600000\0"       \
 370         "kernel_addr_r=0x81000000\0"            \
 371         "kernelheader_size=0x40000\0"           \
 372         "fdt_addr_r=0x90000000\0"               \
 373         "load_addr=0xa0000000\0"                \
 374         "kernel_size=0x2800000\0"               \
 375         "kernel_addr_sd=0x8000\0"               \
 376         "kernel_size_sd=0x14000\0"              \
 377         "console=ttyAMA0,38400n8\0"             \
 378         "mcmemsize=0x70000000\0"                \
 379         "sd_bootcmd=echo Trying load from SD ..;" \
 380         "mmcinfo; mmc read $load_addr "         \
 381         "$kernel_addr_sd $kernel_size_sd && "   \
 382         "bootm $load_addr#$board\0"             \
 383         QSPI_MC_INIT_CMD                                \
 384         BOOTENV                                 \
 385         "boot_scripts=ls2088ardb_boot.scr\0"    \
 386         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 387         "scan_dev_for_boot_part="               \
 388                 "part list ${devtype} ${devnum} devplist; "     \
 389                 "env exists devplist || setenv devplist 1; "    \
 390                 "for distro_bootpart in ${devplist}; do "       \
 391                         "if fstype ${devtype} "                 \
 392                                 "${devnum}:${distro_bootpart} " \
 393                                 "bootfstype; then "             \
 394                                 "run scan_dev_for_boot; "       \
 395                         "fi; "                                  \
 396                 "done\0"                                        \
 397         "boot_a_script="                                        \
 398                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 399                         "${scriptaddr} ${prefix}${script}; "    \
 400                 "env exists secureboot && load ${devtype} "     \
 401                         "${devnum}:${distro_bootpart} "         \
 402                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 403                         "&& esbc_validate ${scripthdraddr};"    \
 404                 "source ${scriptaddr}\0"                        \
 405         "qspi_bootcmd=echo Trying load from qspi..;"            \
 406                 "sf probe && sf read $load_addr "               \
 407                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 408                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 409                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 410                 " bootm $load_addr#$board\0"                    \
 411         "nor_bootcmd=echo Trying load from nor..;"              \
 412                 "cp.b $kernel_addr $load_addr "                 \
 413                 "$kernel_size ; env exists secureboot && "      \
 414                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 415                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 416                 "bootm $load_addr#$board\0"
 417 #else
 418 #define CONFIG_EXTRA_ENV_SETTINGS               \
 419         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 420         "ramdisk_addr=0x800000\0"               \
 421         "ramdisk_size=0x2000000\0"              \
 422         "fdt_high=0xa0000000\0"                 \
 423         "initrd_high=0xffffffffffffffff\0"      \
 424         "fdt_addr=0x64f00000\0"                 \
 425         "kernel_addr=0x581000000\0"             \
 426         "kernel_start=0x1000000\0"              \
 427         "kernelheader_start=0x600000\0"         \
 428         "scriptaddr=0x80000000\0"               \
 429         "scripthdraddr=0x80080000\0"            \
 430         "fdtheader_addr_r=0x80100000\0"         \
 431         "kernelheader_addr_r=0x80200000\0"      \
 432         "kernelheader_addr=0x580600000\0"       \
 433         "kernel_addr_r=0x81000000\0"            \
 434         "kernelheader_size=0x40000\0"           \
 435         "fdt_addr_r=0x90000000\0"               \
 436         "load_addr=0xa0000000\0"                \
 437         "kernel_size=0x2800000\0"               \
 438         "kernel_addr_sd=0x8000\0"               \
 439         "kernel_size_sd=0x14000\0"              \
 440         "console=ttyAMA0,38400n8\0"             \
 441         "mcmemsize=0x70000000\0"                \
 442         "sd_bootcmd=echo Trying load from SD ..;" \
 443         "mmcinfo; mmc read $load_addr "         \
 444         "$kernel_addr_sd $kernel_size_sd && "   \
 445         "bootm $load_addr#$board\0"             \
 446         MC_INIT_CMD                             \
 447         BOOTENV                                 \
 448         "boot_scripts=ls2088ardb_boot.scr\0"    \
 449         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 450         "scan_dev_for_boot_part="               \
 451                 "part list ${devtype} ${devnum} devplist; "     \
 452                 "env exists devplist || setenv devplist 1; "    \
 453                 "for distro_bootpart in ${devplist}; do "       \
 454                         "if fstype ${devtype} "                 \
 455                                 "${devnum}:${distro_bootpart} " \
 456                                 "bootfstype; then "             \
 457                                 "run scan_dev_for_boot; "       \
 458                         "fi; "                                  \
 459                 "done\0"                                        \
 460         "boot_a_script="                                        \
 461                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 462                         "${scriptaddr} ${prefix}${script}; "    \
 463                 "env exists secureboot && load ${devtype} "     \
 464                         "${devnum}:${distro_bootpart} "         \
 465                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 466                         "env exists secureboot "        \
 467                         "&& esbc_validate ${scripthdraddr};"    \
 468                 "source ${scriptaddr}\0"                        \
 469         "qspi_bootcmd=echo Trying load from qspi..;"            \
 470                 "sf probe && sf read $load_addr "               \
 471                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 472                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 473                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 474                 " bootm $load_addr#$board\0"                    \
 475         "nor_bootcmd=echo Trying load from nor..;"              \
 476                 "cp.b $kernel_addr $load_addr "                 \
 477                 "$kernel_size ; env exists secureboot && "      \
 478                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 479                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 480                 "bootm $load_addr#$board\0"
 481 #endif
 482
 483 #ifdef CONFIG_TFABOOT
 484 #define QSPI_NOR_BOOTCOMMAND                                            \
 485                         "sf probe 0:0; "                                \
 486                         "sf read 0x806c0000 0x6c0000 0x40000; "         \
 487                         "env exists mcinitcmd && env exists secureboot "\
 488                         "&& esbc_validate 0x806c0000; "                 \
 489                         "sf read 0x80d00000 0xd00000 0x100000; "        \
 490                         "env exists mcinitcmd && "                      \
 491                         "fsl_mc lazyapply dpl 0x80d00000; "             \
 492                         "run distro_bootcmd;run qspi_bootcmd; "         \
 493                         "env exists secureboot && esbc_halt;"
 494
 495 /* Try to boot an on-SD kernel first, then do normal distro boot */
 496 #define SD_BOOTCOMMAND                                          \
 497                         "env exists mcinitcmd && env exists secureboot "\
 498                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 499                         "&& esbc_validate $load_addr; "                 \
 500                         "env exists mcinitcmd && run mcinitcmd "        \
 501                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 502                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 503                         "run distro_bootcmd;run sd_bootcmd; "           \
 504                         "env exists secureboot && esbc_halt;"
 505
 506 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 507 #define IFC_NOR_BOOTCOMMAND                                             \
 508                         "env exists mcinitcmd && env exists secureboot "\
 509                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 510                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 511                         "run distro_bootcmd;run nor_bootcmd; "          \
 512                         "env exists secureboot && esbc_halt;"
 513 #else
 514 #undef CONFIG_BOOTCOMMAND
 515 #ifdef CONFIG_QSPI_BOOT
 516 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 517 #define CONFIG_BOOTCOMMAND                                              \
 518                         "sf probe 0:0; "                                \
 519                         "sf read 0x806c0000 0x6c0000 0x40000; "         \
 520                         "env exists mcinitcmd && env exists secureboot "\
 521                         "&& esbc_validate 0x806C0000; "                 \
 522                         "sf read 0x80d00000 0xd00000 0x100000; "        \
 523                         "env exists mcinitcmd && "                      \
 524                         "fsl_mc lazyapply dpl 0x80d00000; "             \
 525                         "run distro_bootcmd;run qspi_bootcmd; "         \
 526                         "env exists secureboot && esbc_halt;"
 527 #elif defined(CONFIG_SD_BOOT)
 528 /* Try to boot an on-SD kernel first, then do normal distro boot */
 529 #define CONFIG_BOOTCOMMAND                                              \
 530                         "env exists mcinitcmd && env exists secureboot "\
 531                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 532                         "&& esbc_validate $load_addr; "                 \
 533                         "env exists mcinitcmd && run mcinitcmd "        \
 534                         "&& mmc read 0x88000000 0x6800 0x800 "          \
 535                         "&& fsl_mc lazyapply dpl 0x88000000; "          \
 536                         "run distro_bootcmd;run sd_bootcmd; "           \
 537                         "env exists secureboot && esbc_halt;"
 538 #else
 539 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 540 #define CONFIG_BOOTCOMMAND                                              \
 541                         "env exists mcinitcmd && env exists secureboot "\
 542                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 543                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 544                         "run distro_bootcmd;run nor_bootcmd; "          \
 545                         "env exists secureboot && esbc_halt;"
 546 #endif
 547 #endif
 548
 549 /* MAC/PHY configuration */
 550 #define CORTINA_PHY_ADDR1       0x10
 551 #define CORTINA_PHY_ADDR2       0x11
 552 #define CORTINA_PHY_ADDR3       0x12
 553 #define CORTINA_PHY_ADDR4       0x13
 554 #define AQ_PHY_ADDR1            0x00
 555 #define AQ_PHY_ADDR2            0x01
 556 #define AQ_PHY_ADDR3            0x02
 557 #define AQ_PHY_ADDR4            0x03
 558 #define AQR405_IRQ_MASK         0x36
 559 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 560
 561 #include <asm/fsl_secure_boot.h>
 562
 563 #endif /* __LS2_RDB_H */