Convert CONFIG_SYS_NAND_U_BOOT_LOCATIONS et al to Kconfig
[platform/kernel/u-boot.git] / include / configs / ls2080aqds.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2017, 2019-2021 NXP
4  * Copyright 2015 Freescale Semiconductor
5  */
6
7 #ifndef __LS2_QDS_H
8 #define __LS2_QDS_H
9
10 #include "ls2080a_common.h"
11
12 #ifndef __ASSEMBLY__
13 unsigned long get_board_sys_clk(void);
14 #endif
15
16 #ifdef CONFIG_FSL_QSPI
17 #define CONFIG_QIXIS_I2C_ACCESS
18 #define CONFIG_SYS_I2C_IFDR_DIV         0x7e
19 #endif
20
21 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
22 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
23 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
24
25 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
26 #define SPD_EEPROM_ADDRESS1     0x51
27 #define SPD_EEPROM_ADDRESS2     0x52
28 #define SPD_EEPROM_ADDRESS3     0x53
29 #define SPD_EEPROM_ADDRESS4     0x54
30 #define SPD_EEPROM_ADDRESS5     0x55
31 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
32 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
33 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
34 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
35 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
36 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
37 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
38 #endif
39
40 /* SATA */
41 #define CONFIG_SCSI_AHCI_PLAT
42
43 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
44 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
45
46 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
47 #define CONFIG_SYS_SCSI_MAX_LUN                 1
48 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
49                                                 CONFIG_SYS_SCSI_MAX_LUN)
50
51 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
52 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
53 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
54
55 #define CONFIG_SYS_NOR0_CSPR                                    \
56         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
57         CSPR_PORT_SIZE_16                                       | \
58         CSPR_MSEL_NOR                                           | \
59         CSPR_V)
60 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
61         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
62         CSPR_PORT_SIZE_16                                       | \
63         CSPR_MSEL_NOR                                           | \
64         CSPR_V)
65 #define CONFIG_SYS_NOR1_CSPR                                    \
66         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
67         CSPR_PORT_SIZE_16                                       | \
68         CSPR_MSEL_NOR                                           | \
69         CSPR_V)
70 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
71         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
72         CSPR_PORT_SIZE_16                                       | \
73         CSPR_MSEL_NOR                                           | \
74         CSPR_V)
75 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
76 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
77                                 FTIM0_NOR_TEADC(0x5) | \
78                                 FTIM0_NOR_TEAHC(0x5))
79 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
80                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
81                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
82 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
83                                 FTIM2_NOR_TCH(0x4) | \
84                                 FTIM2_NOR_TWPH(0x0E) | \
85                                 FTIM2_NOR_TWP(0x1c))
86 #define CONFIG_SYS_NOR_FTIM3    0x04000000
87 #define CONFIG_SYS_IFC_CCR      0x01000000
88
89 #ifdef CONFIG_MTD_NOR_FLASH
90 #define CONFIG_SYS_FLASH_QUIET_TEST
91 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
92
93 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
94 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
95 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
96 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
97
98 #define CONFIG_SYS_FLASH_EMPTY_INFO
99 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
100                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
101 #endif
102
103 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
104 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
105
106 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
107 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
108                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
109                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
110                                 | CSPR_V)
111 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
112
113 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
114                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
115                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
116                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
117                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
118                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
119                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
120
121 /* ONFI NAND Flash mode0 Timing Params */
122 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
123                                         FTIM0_NAND_TWP(0x18)   | \
124                                         FTIM0_NAND_TWCHT(0x07) | \
125                                         FTIM0_NAND_TWH(0x0a))
126 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
127                                         FTIM1_NAND_TWBE(0x39)  | \
128                                         FTIM1_NAND_TRR(0x0e)   | \
129                                         FTIM1_NAND_TRP(0x18))
130 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
131                                         FTIM2_NAND_TREH(0x0a) | \
132                                         FTIM2_NAND_TWHRE(0x1e))
133 #define CONFIG_SYS_NAND_FTIM3           0x0
134
135 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
136 #define CONFIG_SYS_MAX_NAND_DEVICE      1
137 #define CONFIG_MTD_NAND_VERIFY_WRITE
138
139 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
140 #define QIXIS_LBMAP_SWITCH              0x06
141 #define QIXIS_LBMAP_MASK                0x0f
142 #define QIXIS_LBMAP_SHIFT               0
143 #define QIXIS_LBMAP_DFLTBANK            0x00
144 #define QIXIS_LBMAP_ALTBANK             0x04
145 #define QIXIS_LBMAP_NAND                0x09
146 #define QIXIS_LBMAP_SD                  0x00
147 #define QIXIS_LBMAP_QSPI                0x0f
148 #define QIXIS_RST_CTL_RESET             0x31
149 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
150 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
151 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
152 #define QIXIS_RCW_SRC_NAND              0x107
153 #define QIXIS_RCW_SRC_SD                0x40
154 #define QIXIS_RCW_SRC_QSPI              0x62
155 #define QIXIS_RST_FORCE_MEM             0x01
156
157 #define CONFIG_SYS_CSPR3_EXT    (0x0)
158 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
159                                 | CSPR_PORT_SIZE_8 \
160                                 | CSPR_MSEL_GPCM \
161                                 | CSPR_V)
162 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
163                                 | CSPR_PORT_SIZE_8 \
164                                 | CSPR_MSEL_GPCM \
165                                 | CSPR_V)
166
167 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
168 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
169 /* QIXIS Timing parameters for IFC CS3 */
170 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
171                                         FTIM0_GPCM_TEADC(0x0e) | \
172                                         FTIM0_GPCM_TEAHC(0x0e))
173 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
174                                         FTIM1_GPCM_TRAD(0x3f))
175 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
176                                         FTIM2_GPCM_TCH(0xf) | \
177                                         FTIM2_GPCM_TWP(0x3E))
178 #define CONFIG_SYS_CS3_FTIM3            0x0
179
180 #if defined(CONFIG_SPL)
181 #if defined(CONFIG_NAND_BOOT)
182 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
183 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR_EARLY
184 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR0_CSPR
185 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
186 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
187 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
188 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
189 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
190 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
191 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
192 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR_EARLY
193 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR1_CSPR
194 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK_EARLY
195 #define CONFIG_SYS_AMASK2_FINAL         CONFIG_SYS_NOR_AMASK
196 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
197 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
198 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
199 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
200 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
201 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
202 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
203 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
204 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
205 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
206 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
207 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
208 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
209
210 #define CONFIG_SPL_PAD_TO               0x20000
211 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 * 1024)
212 #endif
213 #else
214 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
215 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
216 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
217 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
218 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
219 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
220 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
221 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
222 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
223 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
224 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
225 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
226 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
227 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
228 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
229 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
230 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
231 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
232 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
233 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
234 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
235 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
236 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
237 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
238 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
239 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
240 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
241 #endif
242
243 /* Debug Server firmware */
244 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
245 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
246
247 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
248
249 /*
250  * I2C
251  */
252 #define I2C_MUX_PCA_ADDR                0x77
253 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
254
255 /* I2C bus multiplexer */
256 #define I2C_MUX_CH_DEFAULT      0x8
257
258 /* SPI */
259 #ifdef CONFIG_FSL_DSPI
260 #define CONFIG_SPI_FLASH_STMICRO
261 #define CONFIG_SPI_FLASH_SST
262 #define CONFIG_SPI_FLASH_EON
263 #endif
264
265 #ifdef CONFIG_FSL_QSPI
266 #define CONFIG_SPI_FLASH_SPANSION
267 #endif
268 /*
269  * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
270  * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
271  * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
272  */
273 #define FSL_QIXIS_BRDCFG9_QSPI          0x1
274
275 /*
276  * MMC
277  */
278 #ifdef CONFIG_MMC
279 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
280         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
281 #endif
282
283 /*
284  * RTC configuration
285  */
286 #define RTC
287 #define CONFIG_RTC_DS3231               1
288 #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
289 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
290 #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
291
292 /* EEPROM */
293 #define CONFIG_SYS_I2C_EEPROM_NXID
294 #define CONFIG_SYS_EEPROM_BUS_NUM       0
295
296 #define CONFIG_FSL_MEMAC
297
298 #ifdef CONFIG_PCI
299 #define CONFIG_PCI_SCAN_SHOW
300 #endif
301
302 /* Initial environment variables */
303 #undef CONFIG_EXTRA_ENV_SETTINGS
304 #ifdef CONFIG_NXP_ESBC
305 #define CONFIG_EXTRA_ENV_SETTINGS               \
306         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
307         "loadaddr=0x80100000\0"                 \
308         "kernel_addr=0x100000\0"                \
309         "ramdisk_addr=0x800000\0"               \
310         "ramdisk_size=0x2000000\0"              \
311         "fdt_high=0xa0000000\0"                 \
312         "initrd_high=0xffffffffffffffff\0"      \
313         "kernel_start=0x581000000\0"            \
314         "kernel_load=0xa0000000\0"              \
315         "kernel_size=0x2800000\0"               \
316         "mcmemsize=0x40000000\0"                \
317         "mcinitcmd=esbc_validate 0x580640000;"  \
318         "esbc_validate 0x580680000;"            \
319         "fsl_mc start mc 0x580a00000"           \
320         " 0x580e00000 \0"
321 #else
322 #ifdef CONFIG_TFABOOT
323 #define SD_MC_INIT_CMD                          \
324         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
325         "mmc read 0x80e00000 0x7000 0x800;" \
326         "fsl_mc start mc 0x80a00000 0x80e00000\0"
327 #define IFC_MC_INIT_CMD                         \
328         "fsl_mc start mc 0x580a00000" \
329         " 0x580e00000 \0"
330 #define CONFIG_EXTRA_ENV_SETTINGS               \
331         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
332         "loadaddr=0x80100000\0"                 \
333         "loadaddr_sd=0x90100000\0"                 \
334         "kernel_addr=0x581000000\0"                       \
335         "kernel_addr_sd=0x8000\0"                \
336         "ramdisk_addr=0x800000\0"               \
337         "ramdisk_size=0x2000000\0"              \
338         "fdt_high=0xa0000000\0"                 \
339         "initrd_high=0xffffffffffffffff\0"      \
340         "kernel_start=0x581000000\0"            \
341         "kernel_start_sd=0x8000\0"              \
342         "kernel_load=0xa0000000\0"              \
343         "kernel_size=0x2800000\0"               \
344         "kernel_size_sd=0x14000\0"               \
345         "load_addr=0xa0000000\0"                            \
346         "kernelheader_addr=0x580600000\0"       \
347         "kernelheader_addr_r=0x80200000\0"      \
348         "kernelheader_size=0x40000\0"           \
349         "BOARD=ls2088aqds\0" \
350         "mcmemsize=0x70000000 \0" \
351         "scriptaddr=0x80000000\0"               \
352         "scripthdraddr=0x80080000\0"            \
353         IFC_MC_INIT_CMD                         \
354         BOOTENV                                 \
355         "boot_scripts=ls2088aqds_boot.scr\0"    \
356         "boot_script_hdr=hdr_ls2088aqds_bs.out\0"       \
357         "scan_dev_for_boot_part="               \
358                 "part list ${devtype} ${devnum} devplist; "     \
359                 "env exists devplist || setenv devplist 1; "    \
360                 "for distro_bootpart in ${devplist}; do "       \
361                         "if fstype ${devtype} "                 \
362                                 "${devnum}:${distro_bootpart} " \
363                                 "bootfstype; then "             \
364                                 "run scan_dev_for_boot; "       \
365                         "fi; "                                  \
366                 "done\0"                                        \
367         "boot_a_script="                                        \
368                 "load ${devtype} ${devnum}:${distro_bootpart} " \
369                         "${scriptaddr} ${prefix}${script}; "    \
370                 "env exists secureboot && load ${devtype} "     \
371                         "${devnum}:${distro_bootpart} "         \
372                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
373                         "&& esbc_validate ${scripthdraddr};"    \
374                 "source ${scriptaddr}\0"                        \
375         "nor_bootcmd=echo Trying load from nor..;"              \
376                 "cp.b $kernel_addr $load_addr "                 \
377                 "$kernel_size ; env exists secureboot && "      \
378                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
379                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
380                 "bootm $load_addr#$BOARD\0"     \
381         "sd_bootcmd=echo Trying load from SD ..;" \
382         "mmcinfo; mmc read $load_addr "         \
383         "$kernel_addr_sd $kernel_size_sd && "   \
384         "bootm $load_addr#$BOARD\0"
385 #elif defined(CONFIG_SD_BOOT)
386 #define CONFIG_EXTRA_ENV_SETTINGS               \
387         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
388         "loadaddr=0x90100000\0"                 \
389         "kernel_addr=0x800\0"                \
390         "ramdisk_addr=0x800000\0"               \
391         "ramdisk_size=0x2000000\0"              \
392         "fdt_high=0xa0000000\0"                 \
393         "initrd_high=0xffffffffffffffff\0"      \
394         "kernel_start=0x8000\0"              \
395         "kernel_load=0xa0000000\0"              \
396         "kernel_size=0x14000\0"               \
397         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
398         "mmc read 0x80e00000 0x7000 0x800;" \
399         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
400         "mcmemsize=0x70000000 \0"
401 #else
402 #define CONFIG_EXTRA_ENV_SETTINGS               \
403         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
404         "loadaddr=0x80100000\0"                 \
405         "kernel_addr=0x100000\0"                \
406         "ramdisk_addr=0x800000\0"               \
407         "ramdisk_size=0x2000000\0"              \
408         "fdt_high=0xa0000000\0"                 \
409         "initrd_high=0xffffffffffffffff\0"      \
410         "kernel_start=0x581000000\0"            \
411         "kernel_load=0xa0000000\0"              \
412         "kernel_size=0x2800000\0"               \
413         "mcmemsize=0x40000000\0"                \
414         "mcinitcmd=fsl_mc start mc 0x580a00000" \
415         " 0x580e00000 \0"
416 #endif /* CONFIG_TFABOOT */
417 #endif /* CONFIG_NXP_ESBC */
418
419 #ifdef CONFIG_TFABOOT
420 #define BOOT_TARGET_DEVICES(func) \
421         func(USB, usb, 0) \
422         func(MMC, mmc, 0) \
423         func(SCSI, scsi, 0) \
424         func(DHCP, dhcp, na)
425 #include <config_distro_bootcmd.h>
426
427 #define SD_BOOTCOMMAND                                          \
428                         "env exists mcinitcmd && env exists secureboot "\
429                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
430                         "&& esbc_validate $load_addr; "                 \
431                         "env exists mcinitcmd && run mcinitcmd "        \
432                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
433                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
434                         "run distro_bootcmd;run sd_bootcmd; "           \
435                         "env exists secureboot && esbc_halt;"
436
437 #define IFC_NOR_BOOTCOMMAND                                             \
438                         "env exists mcinitcmd && env exists secureboot "\
439                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
440                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
441                         "run distro_bootcmd;run nor_bootcmd; "          \
442                         "env exists secureboot && esbc_halt;"
443 #endif
444
445 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
446 #define CONFIG_FSL_MEMAC
447 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
448 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
449 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
450 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
451
452 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
453 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
454 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
455 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
456 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
457 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
458 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
459 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
460 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
461 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
462 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
463 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
464 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
465 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
466 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
467 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
468
469 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
470
471 #endif
472
473 #include <asm/fsl_secure_boot.h>
474
475 #endif /* __LS2_QDS_H */