include/configs/ls2080aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2021 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_QDS_H
   8 #define __LS2_QDS_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #ifdef CONFIG_FSL_QSPI
  13 #define CONFIG_QIXIS_I2C_ACCESS
  14 #define CONFIG_SYS_I2C_IFDR_DIV         0x7e
  15 #endif
  16
  17 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
  18 #define COUNTER_FREQUENCY_REAL          (get_board_sys_clk()/4)
  19
  20 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  21 #define SPD_EEPROM_ADDRESS1     0x51
  22 #define SPD_EEPROM_ADDRESS2     0x52
  23 #define SPD_EEPROM_ADDRESS3     0x53
  24 #define SPD_EEPROM_ADDRESS4     0x54
  25 #define SPD_EEPROM_ADDRESS5     0x55
  26 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  27 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  28 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  29 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  30 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  31 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  32 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  33 #endif
  34
  35 /* SATA */
  36 #define CONFIG_SCSI_AHCI_PLAT
  37
  38 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  39 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  40
  41 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  42 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  43
  44 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  45 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  46 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  47
  48 #define CONFIG_SYS_NOR0_CSPR                                    \
  49         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  50         CSPR_PORT_SIZE_16                                       | \
  51         CSPR_MSEL_NOR                                           | \
  52         CSPR_V)
  53 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  54         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  55         CSPR_PORT_SIZE_16                                       | \
  56         CSPR_MSEL_NOR                                           | \
  57         CSPR_V)
  58 #define CONFIG_SYS_NOR1_CSPR                                    \
  59         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  60         CSPR_PORT_SIZE_16                                       | \
  61         CSPR_MSEL_NOR                                           | \
  62         CSPR_V)
  63 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  64         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  65         CSPR_PORT_SIZE_16                                       | \
  66         CSPR_MSEL_NOR                                           | \
  67         CSPR_V)
  68 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  69 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  70                                 FTIM0_NOR_TEADC(0x5) | \
  71                                 FTIM0_NOR_TEAHC(0x5))
  72 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  73                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  74                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  75 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  76                                 FTIM2_NOR_TCH(0x4) | \
  77                                 FTIM2_NOR_TWPH(0x0E) | \
  78                                 FTIM2_NOR_TWP(0x1c))
  79 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  80 #define CONFIG_SYS_IFC_CCR      0x01000000
  81
  82 #ifdef CONFIG_MTD_NOR_FLASH
  83 #define CONFIG_SYS_FLASH_QUIET_TEST
  84 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  85
  86 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  87 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  88 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  89
  90 #define CONFIG_SYS_FLASH_EMPTY_INFO
  91 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  92                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  93 #endif
  94
  95 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  96 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  97
  98 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  99 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 100                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 101                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 102                                 | CSPR_V)
 103 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 104
 105 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 106                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 107                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 108                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 109                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 110                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 111                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 112
 113 /* ONFI NAND Flash mode0 Timing Params */
 114 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 115                                         FTIM0_NAND_TWP(0x18)   | \
 116                                         FTIM0_NAND_TWCHT(0x07) | \
 117                                         FTIM0_NAND_TWH(0x0a))
 118 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 119                                         FTIM1_NAND_TWBE(0x39)  | \
 120                                         FTIM1_NAND_TRR(0x0e)   | \
 121                                         FTIM1_NAND_TRP(0x18))
 122 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 123                                         FTIM2_NAND_TREH(0x0a) | \
 124                                         FTIM2_NAND_TWHRE(0x1e))
 125 #define CONFIG_SYS_NAND_FTIM3           0x0
 126
 127 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 128 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 129 #define CONFIG_MTD_NAND_VERIFY_WRITE
 130
 131 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 132 #define QIXIS_LBMAP_SWITCH              0x06
 133 #define QIXIS_LBMAP_MASK                0x0f
 134 #define QIXIS_LBMAP_SHIFT               0
 135 #define QIXIS_LBMAP_DFLTBANK            0x00
 136 #define QIXIS_LBMAP_ALTBANK             0x04
 137 #define QIXIS_LBMAP_NAND                0x09
 138 #define QIXIS_LBMAP_SD                  0x00
 139 #define QIXIS_LBMAP_QSPI                0x0f
 140 #define QIXIS_RST_CTL_RESET             0x31
 141 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 142 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 143 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 144 #define QIXIS_RCW_SRC_NAND              0x107
 145 #define QIXIS_RCW_SRC_SD                0x40
 146 #define QIXIS_RCW_SRC_QSPI              0x62
 147 #define QIXIS_RST_FORCE_MEM             0x01
 148
 149 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 150 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 151                                 | CSPR_PORT_SIZE_8 \
 152                                 | CSPR_MSEL_GPCM \
 153                                 | CSPR_V)
 154 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 155                                 | CSPR_PORT_SIZE_8 \
 156                                 | CSPR_MSEL_GPCM \
 157                                 | CSPR_V)
 158
 159 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 160 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 161 /* QIXIS Timing parameters for IFC CS3 */
 162 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 163                                         FTIM0_GPCM_TEADC(0x0e) | \
 164                                         FTIM0_GPCM_TEAHC(0x0e))
 165 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 166                                         FTIM1_GPCM_TRAD(0x3f))
 167 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 168                                         FTIM2_GPCM_TCH(0xf) | \
 169                                         FTIM2_GPCM_TWP(0x3E))
 170 #define CONFIG_SYS_CS3_FTIM3            0x0
 171
 172 #if defined(CONFIG_SPL)
 173 #if defined(CONFIG_NAND_BOOT)
 174 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 175 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR_EARLY
 176 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR0_CSPR
 177 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 178 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 179 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 180 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 181 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 182 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 183 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 184 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR_EARLY
 185 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR1_CSPR
 186 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK_EARLY
 187 #define CONFIG_SYS_AMASK2_FINAL         CONFIG_SYS_NOR_AMASK
 188 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 189 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 190 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 191 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 192 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 193 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 194 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 195 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 196 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 197 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 198 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 199 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 200 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 201
 202 #define CONFIG_SPL_PAD_TO               0x20000
 203 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 * 1024)
 204 #endif
 205 #else
 206 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 207 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 208 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 209 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 210 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 211 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 212 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 213 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 214 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 215 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 216 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 217 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 218 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 219 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 220 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 221 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 222 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 223 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 224 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 225 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 226 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 227 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 228 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 229 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 230 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 231 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 232 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 233 #endif
 234
 235 /* Debug Server firmware */
 236 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 237 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 238
 239 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 240
 241 /*
 242  * I2C
 243  */
 244 #define I2C_MUX_PCA_ADDR                0x77
 245 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 246
 247 /* I2C bus multiplexer */
 248 #define I2C_MUX_CH_DEFAULT      0x8
 249
 250 /* SPI */
 251
 252 /*
 253  * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
 254  * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
 255  * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
 256  */
 257 #define FSL_QIXIS_BRDCFG9_QSPI          0x1
 258
 259 /*
 260  * MMC
 261  */
 262 #ifdef CONFIG_MMC
 263 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
 264         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
 265 #endif
 266
 267 /*
 268  * RTC configuration
 269  */
 270 #define RTC
 271 #define CONFIG_RTC_DS3231               1
 272 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 273
 274 /* EEPROM */
 275 #define CONFIG_SYS_I2C_EEPROM_NXID
 276 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 277
 278 #define CONFIG_FSL_MEMAC
 279
 280 #ifdef CONFIG_PCI
 281 #define CONFIG_PCI_SCAN_SHOW
 282 #endif
 283
 284 /* Initial environment variables */
 285 #undef CONFIG_EXTRA_ENV_SETTINGS
 286 #ifdef CONFIG_NXP_ESBC
 287 #define CONFIG_EXTRA_ENV_SETTINGS               \
 288         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 289         "loadaddr=0x80100000\0"                 \
 290         "kernel_addr=0x100000\0"                \
 291         "ramdisk_addr=0x800000\0"               \
 292         "ramdisk_size=0x2000000\0"              \
 293         "fdt_high=0xa0000000\0"                 \
 294         "initrd_high=0xffffffffffffffff\0"      \
 295         "kernel_start=0x581000000\0"            \
 296         "kernel_load=0xa0000000\0"              \
 297         "kernel_size=0x2800000\0"               \
 298         "mcmemsize=0x40000000\0"                \
 299         "mcinitcmd=esbc_validate 0x580640000;"  \
 300         "esbc_validate 0x580680000;"            \
 301         "fsl_mc start mc 0x580a00000"           \
 302         " 0x580e00000 \0"
 303 #else
 304 #ifdef CONFIG_TFABOOT
 305 #define SD_MC_INIT_CMD                          \
 306         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 307         "mmc read 0x80e00000 0x7000 0x800;" \
 308         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 309 #define IFC_MC_INIT_CMD                         \
 310         "fsl_mc start mc 0x580a00000" \
 311         " 0x580e00000 \0"
 312 #define CONFIG_EXTRA_ENV_SETTINGS               \
 313         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 314         "loadaddr=0x80100000\0"                 \
 315         "loadaddr_sd=0x90100000\0"                 \
 316         "kernel_addr=0x581000000\0"                       \
 317         "kernel_addr_sd=0x8000\0"                \
 318         "ramdisk_addr=0x800000\0"               \
 319         "ramdisk_size=0x2000000\0"              \
 320         "fdt_high=0xa0000000\0"                 \
 321         "initrd_high=0xffffffffffffffff\0"      \
 322         "kernel_start=0x581000000\0"            \
 323         "kernel_start_sd=0x8000\0"              \
 324         "kernel_load=0xa0000000\0"              \
 325         "kernel_size=0x2800000\0"               \
 326         "kernel_size_sd=0x14000\0"               \
 327         "load_addr=0xa0000000\0"                            \
 328         "kernelheader_addr=0x580600000\0"       \
 329         "kernelheader_addr_r=0x80200000\0"      \
 330         "kernelheader_size=0x40000\0"           \
 331         "BOARD=ls2088aqds\0" \
 332         "mcmemsize=0x70000000 \0" \
 333         "scriptaddr=0x80000000\0"               \
 334         "scripthdraddr=0x80080000\0"            \
 335         IFC_MC_INIT_CMD                         \
 336         BOOTENV                                 \
 337         "boot_scripts=ls2088aqds_boot.scr\0"    \
 338         "boot_script_hdr=hdr_ls2088aqds_bs.out\0"       \
 339         "scan_dev_for_boot_part="               \
 340                 "part list ${devtype} ${devnum} devplist; "     \
 341                 "env exists devplist || setenv devplist 1; "    \
 342                 "for distro_bootpart in ${devplist}; do "       \
 343                         "if fstype ${devtype} "                 \
 344                                 "${devnum}:${distro_bootpart} " \
 345                                 "bootfstype; then "             \
 346                                 "run scan_dev_for_boot; "       \
 347                         "fi; "                                  \
 348                 "done\0"                                        \
 349         "boot_a_script="                                        \
 350                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 351                         "${scriptaddr} ${prefix}${script}; "    \
 352                 "env exists secureboot && load ${devtype} "     \
 353                         "${devnum}:${distro_bootpart} "         \
 354                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 355                         "&& esbc_validate ${scripthdraddr};"    \
 356                 "source ${scriptaddr}\0"                        \
 357         "nor_bootcmd=echo Trying load from nor..;"              \
 358                 "cp.b $kernel_addr $load_addr "                 \
 359                 "$kernel_size ; env exists secureboot && "      \
 360                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 361                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 362                 "bootm $load_addr#$BOARD\0"     \
 363         "sd_bootcmd=echo Trying load from SD ..;" \
 364         "mmcinfo; mmc read $load_addr "         \
 365         "$kernel_addr_sd $kernel_size_sd && "   \
 366         "bootm $load_addr#$BOARD\0"
 367 #elif defined(CONFIG_SD_BOOT)
 368 #define CONFIG_EXTRA_ENV_SETTINGS               \
 369         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 370         "loadaddr=0x90100000\0"                 \
 371         "kernel_addr=0x800\0"                \
 372         "ramdisk_addr=0x800000\0"               \
 373         "ramdisk_size=0x2000000\0"              \
 374         "fdt_high=0xa0000000\0"                 \
 375         "initrd_high=0xffffffffffffffff\0"      \
 376         "kernel_start=0x8000\0"              \
 377         "kernel_load=0xa0000000\0"              \
 378         "kernel_size=0x14000\0"               \
 379         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 380         "mmc read 0x80e00000 0x7000 0x800;" \
 381         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 382         "mcmemsize=0x70000000 \0"
 383 #else
 384 #define CONFIG_EXTRA_ENV_SETTINGS               \
 385         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 386         "loadaddr=0x80100000\0"                 \
 387         "kernel_addr=0x100000\0"                \
 388         "ramdisk_addr=0x800000\0"               \
 389         "ramdisk_size=0x2000000\0"              \
 390         "fdt_high=0xa0000000\0"                 \
 391         "initrd_high=0xffffffffffffffff\0"      \
 392         "kernel_start=0x581000000\0"            \
 393         "kernel_load=0xa0000000\0"              \
 394         "kernel_size=0x2800000\0"               \
 395         "mcmemsize=0x40000000\0"                \
 396         "mcinitcmd=fsl_mc start mc 0x580a00000" \
 397         " 0x580e00000 \0"
 398 #endif /* CONFIG_TFABOOT */
 399 #endif /* CONFIG_NXP_ESBC */
 400
 401 #ifdef CONFIG_TFABOOT
 402 #define BOOT_TARGET_DEVICES(func) \
 403         func(USB, usb, 0) \
 404         func(MMC, mmc, 0) \
 405         func(SCSI, scsi, 0) \
 406         func(DHCP, dhcp, na)
 407 #include <config_distro_bootcmd.h>
 408
 409 #define SD_BOOTCOMMAND                                          \
 410                         "env exists mcinitcmd && env exists secureboot "\
 411                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 412                         "&& esbc_validate $load_addr; "                 \
 413                         "env exists mcinitcmd && run mcinitcmd "        \
 414                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 415                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 416                         "run distro_bootcmd;run sd_bootcmd; "           \
 417                         "env exists secureboot && esbc_halt;"
 418
 419 #define IFC_NOR_BOOTCOMMAND                                             \
 420                         "env exists mcinitcmd && env exists secureboot "\
 421                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 422                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 423                         "run distro_bootcmd;run nor_bootcmd; "          \
 424                         "env exists secureboot && esbc_halt;"
 425 #endif
 426
 427 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 428 #define CONFIG_FSL_MEMAC
 429 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 430 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 431 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 432 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 433
 434 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 435 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 436 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 437 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 438 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 439 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 440 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 441 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 442 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 443 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 444 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 445 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 446 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 447 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 448 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 449 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 450
 451 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 452
 453 #endif
 454
 455 #include <asm/fsl_secure_boot.h>
 456
 457 #endif /* __LS2_QDS_H */