include/configs/ls2080aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2021 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_QDS_H
   8 #define __LS2_QDS_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #ifndef __ASSEMBLY__
  13 unsigned long get_board_sys_clk(void);
  14 #endif
  15
  16 #ifdef CONFIG_FSL_QSPI
  17 #define CONFIG_QIXIS_I2C_ACCESS
  18 #define CONFIG_SYS_I2C_IFDR_DIV         0x7e
  19 #endif
  20
  21 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
  22 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  23 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  24
  25 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  26 #define SPD_EEPROM_ADDRESS1     0x51
  27 #define SPD_EEPROM_ADDRESS2     0x52
  28 #define SPD_EEPROM_ADDRESS3     0x53
  29 #define SPD_EEPROM_ADDRESS4     0x54
  30 #define SPD_EEPROM_ADDRESS5     0x55
  31 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  32 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  33 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  34 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  35 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  36 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  37 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  38 #endif
  39
  40 /* SATA */
  41 #define CONFIG_SCSI_AHCI_PLAT
  42
  43 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  44 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  45
  46 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  47 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  48 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  49                                                 CONFIG_SYS_SCSI_MAX_LUN)
  50
  51 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  52 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  53 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  54
  55 #define CONFIG_SYS_NOR0_CSPR                                    \
  56         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  57         CSPR_PORT_SIZE_16                                       | \
  58         CSPR_MSEL_NOR                                           | \
  59         CSPR_V)
  60 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  61         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  62         CSPR_PORT_SIZE_16                                       | \
  63         CSPR_MSEL_NOR                                           | \
  64         CSPR_V)
  65 #define CONFIG_SYS_NOR1_CSPR                                    \
  66         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  67         CSPR_PORT_SIZE_16                                       | \
  68         CSPR_MSEL_NOR                                           | \
  69         CSPR_V)
  70 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  71         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  72         CSPR_PORT_SIZE_16                                       | \
  73         CSPR_MSEL_NOR                                           | \
  74         CSPR_V)
  75 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  76 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  77                                 FTIM0_NOR_TEADC(0x5) | \
  78                                 FTIM0_NOR_TEAHC(0x5))
  79 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  80                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  81                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  82 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  83                                 FTIM2_NOR_TCH(0x4) | \
  84                                 FTIM2_NOR_TWPH(0x0E) | \
  85                                 FTIM2_NOR_TWP(0x1c))
  86 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  87 #define CONFIG_SYS_IFC_CCR      0x01000000
  88
  89 #ifdef CONFIG_MTD_NOR_FLASH
  90 #define CONFIG_SYS_FLASH_QUIET_TEST
  91 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  92
  93 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
  94 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  95 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  96 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  97
  98 #define CONFIG_SYS_FLASH_EMPTY_INFO
  99 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
 100                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
 101 #endif
 102
 103 #define CONFIG_NAND_FSL_IFC
 104 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 105 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 106
 107 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 108 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 109                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 110                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 111                                 | CSPR_V)
 112 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 113
 114 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 115                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 116                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 117                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 118                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 119                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 120                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 121
 122 #define CONFIG_SYS_NAND_ONFI_DETECTION
 123
 124 /* ONFI NAND Flash mode0 Timing Params */
 125 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 126                                         FTIM0_NAND_TWP(0x18)   | \
 127                                         FTIM0_NAND_TWCHT(0x07) | \
 128                                         FTIM0_NAND_TWH(0x0a))
 129 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 130                                         FTIM1_NAND_TWBE(0x39)  | \
 131                                         FTIM1_NAND_TRR(0x0e)   | \
 132                                         FTIM1_NAND_TRP(0x18))
 133 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 134                                         FTIM2_NAND_TREH(0x0a) | \
 135                                         FTIM2_NAND_TWHRE(0x1e))
 136 #define CONFIG_SYS_NAND_FTIM3           0x0
 137
 138 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 139 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 140 #define CONFIG_MTD_NAND_VERIFY_WRITE
 141
 142 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 143 #define QIXIS_LBMAP_SWITCH              0x06
 144 #define QIXIS_LBMAP_MASK                0x0f
 145 #define QIXIS_LBMAP_SHIFT               0
 146 #define QIXIS_LBMAP_DFLTBANK            0x00
 147 #define QIXIS_LBMAP_ALTBANK             0x04
 148 #define QIXIS_LBMAP_NAND                0x09
 149 #define QIXIS_LBMAP_SD                  0x00
 150 #define QIXIS_LBMAP_QSPI                0x0f
 151 #define QIXIS_RST_CTL_RESET             0x31
 152 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 153 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 154 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 155 #define QIXIS_RCW_SRC_NAND              0x107
 156 #define QIXIS_RCW_SRC_SD                0x40
 157 #define QIXIS_RCW_SRC_QSPI              0x62
 158 #define QIXIS_RST_FORCE_MEM             0x01
 159
 160 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 161 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 162                                 | CSPR_PORT_SIZE_8 \
 163                                 | CSPR_MSEL_GPCM \
 164                                 | CSPR_V)
 165 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 166                                 | CSPR_PORT_SIZE_8 \
 167                                 | CSPR_MSEL_GPCM \
 168                                 | CSPR_V)
 169
 170 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 171 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 172 /* QIXIS Timing parameters for IFC CS3 */
 173 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 174                                         FTIM0_GPCM_TEADC(0x0e) | \
 175                                         FTIM0_GPCM_TEAHC(0x0e))
 176 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 177                                         FTIM1_GPCM_TRAD(0x3f))
 178 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 179                                         FTIM2_GPCM_TCH(0xf) | \
 180                                         FTIM2_GPCM_TWP(0x3E))
 181 #define CONFIG_SYS_CS3_FTIM3            0x0
 182
 183 #if defined(CONFIG_SPL)
 184 #if defined(CONFIG_NAND_BOOT)
 185 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 186 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR_EARLY
 187 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR0_CSPR
 188 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 189 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 190 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 191 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 192 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 193 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 194 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 195 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR_EARLY
 196 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR1_CSPR
 197 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK_EARLY
 198 #define CONFIG_SYS_AMASK2_FINAL         CONFIG_SYS_NOR_AMASK
 199 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 200 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 201 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 202 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 203 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 204 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 205 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 206 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 207 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 208 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 209 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 210 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 211 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 212
 213 #define CONFIG_SPL_PAD_TO               0x20000
 214 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 * 1024)
 215 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 * 1024)
 216 #endif
 217 #else
 218 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 219 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 220 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 221 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 222 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 223 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 224 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 225 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 226 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 227 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 228 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 229 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 230 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 231 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 232 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 233 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 234 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 235 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 236 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 237 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 238 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 239 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 240 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 241 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 242 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 243 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 244 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 245 #endif
 246
 247 /* Debug Server firmware */
 248 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 249 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 250
 251 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 252
 253 /*
 254  * I2C
 255  */
 256 #define I2C_MUX_PCA_ADDR                0x77
 257 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 258
 259 /* I2C bus multiplexer */
 260 #define I2C_MUX_CH_DEFAULT      0x8
 261
 262 /* SPI */
 263 #ifdef CONFIG_FSL_DSPI
 264 #define CONFIG_SPI_FLASH_STMICRO
 265 #define CONFIG_SPI_FLASH_SST
 266 #define CONFIG_SPI_FLASH_EON
 267 #endif
 268
 269 #ifdef CONFIG_FSL_QSPI
 270 #define CONFIG_SPI_FLASH_SPANSION
 271 #endif
 272 /*
 273  * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
 274  * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
 275  * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
 276  */
 277 #define FSL_QIXIS_BRDCFG9_QSPI          0x1
 278
 279 /*
 280  * MMC
 281  */
 282 #ifdef CONFIG_MMC
 283 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
 284         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
 285 #endif
 286
 287 /*
 288  * RTC configuration
 289  */
 290 #define RTC
 291 #define CONFIG_RTC_DS3231               1
 292 #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
 293 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 294 #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
 295
 296 /* EEPROM */
 297 #define CONFIG_SYS_I2C_EEPROM_NXID
 298 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 299
 300 #define CONFIG_FSL_MEMAC
 301
 302 #ifdef CONFIG_PCI
 303 #define CONFIG_PCI_SCAN_SHOW
 304 #endif
 305
 306 /* Initial environment variables */
 307 #undef CONFIG_EXTRA_ENV_SETTINGS
 308 #ifdef CONFIG_NXP_ESBC
 309 #define CONFIG_EXTRA_ENV_SETTINGS               \
 310         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 311         "loadaddr=0x80100000\0"                 \
 312         "kernel_addr=0x100000\0"                \
 313         "ramdisk_addr=0x800000\0"               \
 314         "ramdisk_size=0x2000000\0"              \
 315         "fdt_high=0xa0000000\0"                 \
 316         "initrd_high=0xffffffffffffffff\0"      \
 317         "kernel_start=0x581000000\0"            \
 318         "kernel_load=0xa0000000\0"              \
 319         "kernel_size=0x2800000\0"               \
 320         "mcmemsize=0x40000000\0"                \
 321         "mcinitcmd=esbc_validate 0x580640000;"  \
 322         "esbc_validate 0x580680000;"            \
 323         "fsl_mc start mc 0x580a00000"           \
 324         " 0x580e00000 \0"
 325 #else
 326 #ifdef CONFIG_TFABOOT
 327 #define SD_MC_INIT_CMD                          \
 328         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 329         "mmc read 0x80e00000 0x7000 0x800;" \
 330         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 331 #define IFC_MC_INIT_CMD                         \
 332         "fsl_mc start mc 0x580a00000" \
 333         " 0x580e00000 \0"
 334 #define CONFIG_EXTRA_ENV_SETTINGS               \
 335         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 336         "loadaddr=0x80100000\0"                 \
 337         "loadaddr_sd=0x90100000\0"                 \
 338         "kernel_addr=0x581000000\0"                       \
 339         "kernel_addr_sd=0x8000\0"                \
 340         "ramdisk_addr=0x800000\0"               \
 341         "ramdisk_size=0x2000000\0"              \
 342         "fdt_high=0xa0000000\0"                 \
 343         "initrd_high=0xffffffffffffffff\0"      \
 344         "kernel_start=0x581000000\0"            \
 345         "kernel_start_sd=0x8000\0"              \
 346         "kernel_load=0xa0000000\0"              \
 347         "kernel_size=0x2800000\0"               \
 348         "kernel_size_sd=0x14000\0"               \
 349         "load_addr=0xa0000000\0"                            \
 350         "kernelheader_addr=0x580600000\0"       \
 351         "kernelheader_addr_r=0x80200000\0"      \
 352         "kernelheader_size=0x40000\0"           \
 353         "BOARD=ls2088aqds\0" \
 354         "mcmemsize=0x70000000 \0" \
 355         "scriptaddr=0x80000000\0"               \
 356         "scripthdraddr=0x80080000\0"            \
 357         IFC_MC_INIT_CMD                         \
 358         BOOTENV                                 \
 359         "boot_scripts=ls2088aqds_boot.scr\0"    \
 360         "boot_script_hdr=hdr_ls2088aqds_bs.out\0"       \
 361         "scan_dev_for_boot_part="               \
 362                 "part list ${devtype} ${devnum} devplist; "     \
 363                 "env exists devplist || setenv devplist 1; "    \
 364                 "for distro_bootpart in ${devplist}; do "       \
 365                         "if fstype ${devtype} "                 \
 366                                 "${devnum}:${distro_bootpart} " \
 367                                 "bootfstype; then "             \
 368                                 "run scan_dev_for_boot; "       \
 369                         "fi; "                                  \
 370                 "done\0"                                        \
 371         "boot_a_script="                                        \
 372                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 373                         "${scriptaddr} ${prefix}${script}; "    \
 374                 "env exists secureboot && load ${devtype} "     \
 375                         "${devnum}:${distro_bootpart} "         \
 376                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 377                         "&& esbc_validate ${scripthdraddr};"    \
 378                 "source ${scriptaddr}\0"                        \
 379         "nor_bootcmd=echo Trying load from nor..;"              \
 380                 "cp.b $kernel_addr $load_addr "                 \
 381                 "$kernel_size ; env exists secureboot && "      \
 382                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 383                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 384                 "bootm $load_addr#$BOARD\0"     \
 385         "sd_bootcmd=echo Trying load from SD ..;" \
 386         "mmcinfo; mmc read $load_addr "         \
 387         "$kernel_addr_sd $kernel_size_sd && "   \
 388         "bootm $load_addr#$BOARD\0"
 389 #elif defined(CONFIG_SD_BOOT)
 390 #define CONFIG_EXTRA_ENV_SETTINGS               \
 391         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 392         "loadaddr=0x90100000\0"                 \
 393         "kernel_addr=0x800\0"                \
 394         "ramdisk_addr=0x800000\0"               \
 395         "ramdisk_size=0x2000000\0"              \
 396         "fdt_high=0xa0000000\0"                 \
 397         "initrd_high=0xffffffffffffffff\0"      \
 398         "kernel_start=0x8000\0"              \
 399         "kernel_load=0xa0000000\0"              \
 400         "kernel_size=0x14000\0"               \
 401         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 402         "mmc read 0x80e00000 0x7000 0x800;" \
 403         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 404         "mcmemsize=0x70000000 \0"
 405 #else
 406 #define CONFIG_EXTRA_ENV_SETTINGS               \
 407         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 408         "loadaddr=0x80100000\0"                 \
 409         "kernel_addr=0x100000\0"                \
 410         "ramdisk_addr=0x800000\0"               \
 411         "ramdisk_size=0x2000000\0"              \
 412         "fdt_high=0xa0000000\0"                 \
 413         "initrd_high=0xffffffffffffffff\0"      \
 414         "kernel_start=0x581000000\0"            \
 415         "kernel_load=0xa0000000\0"              \
 416         "kernel_size=0x2800000\0"               \
 417         "mcmemsize=0x40000000\0"                \
 418         "mcinitcmd=fsl_mc start mc 0x580a00000" \
 419         " 0x580e00000 \0"
 420 #endif /* CONFIG_TFABOOT */
 421 #endif /* CONFIG_NXP_ESBC */
 422
 423 #ifdef CONFIG_TFABOOT
 424 #define BOOT_TARGET_DEVICES(func) \
 425         func(USB, usb, 0) \
 426         func(MMC, mmc, 0) \
 427         func(SCSI, scsi, 0) \
 428         func(DHCP, dhcp, na)
 429 #include <config_distro_bootcmd.h>
 430
 431 #define SD_BOOTCOMMAND                                          \
 432                         "env exists mcinitcmd && env exists secureboot "\
 433                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 434                         "&& esbc_validate $load_addr; "                 \
 435                         "env exists mcinitcmd && run mcinitcmd "        \
 436                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 437                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 438                         "run distro_bootcmd;run sd_bootcmd; "           \
 439                         "env exists secureboot && esbc_halt;"
 440
 441 #define IFC_NOR_BOOTCOMMAND                                             \
 442                         "env exists mcinitcmd && env exists secureboot "\
 443                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 444                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 445                         "run distro_bootcmd;run nor_bootcmd; "          \
 446                         "env exists secureboot && esbc_halt;"
 447 #endif
 448
 449 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 450 #define CONFIG_FSL_MEMAC
 451 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 452 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 453 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 454 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 455
 456 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 457 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 458 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 459 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 460 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 461 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 462 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 463 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 464 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 465 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 466 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 467 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 468 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 469 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 470 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 471 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 472
 473 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 474
 475 #endif
 476
 477 #include <asm/fsl_secure_boot.h>
 478
 479 #endif /* __LS2_QDS_H */