1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_RDB_H
7 #define __LS1088A_RDB_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_TFABOOT) || \
12 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
16 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
18 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
19 #define SPD_EEPROM_ADDRESS 0x51
22 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
23 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
24 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
25 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
27 #define CONFIG_SYS_NOR0_CSPR \
28 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
32 #define CONFIG_SYS_NOR0_CSPR_EARLY \
33 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
37 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
38 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
39 FTIM0_NOR_TEADC(0x1) | \
41 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
42 FTIM1_NOR_TRAD_NOR(0x1))
43 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
44 FTIM2_NOR_TCH(0x0) | \
46 #define CONFIG_SYS_NOR_FTIM3 0x04000000
47 #define CONFIG_SYS_IFC_CCR 0x01000000
50 #define CONFIG_SYS_FLASH_QUIET_TEST
51 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
53 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
55 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
59 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
60 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
62 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
63 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
64 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
65 | CSPR_MSEL_NAND /* MSEL = NAND */ \
67 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
69 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
70 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
71 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
72 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
73 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
74 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
75 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
77 /* ONFI NAND Flash mode0 Timing Params */
78 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
79 FTIM0_NAND_TWP(0x18) | \
80 FTIM0_NAND_TWCHT(0x07) | \
82 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
83 FTIM1_NAND_TWBE(0x39) | \
84 FTIM1_NAND_TRR(0x0e) | \
86 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
87 FTIM2_NAND_TREH(0x0a) | \
88 FTIM2_NAND_TWHRE(0x1e))
89 #define CONFIG_SYS_NAND_FTIM3 0x0
91 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
92 #define CONFIG_SYS_MAX_NAND_DEVICE 1
93 #define CONFIG_MTD_NAND_VERIFY_WRITE
95 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
96 #define QIXIS_BRDCFG4_OFFSET 0x54
97 #define QIXIS_LBMAP_SWITCH 2
98 #define QIXIS_QMAP_MASK 0xe0
99 #define QIXIS_QMAP_SHIFT 5
100 #define QIXIS_LBMAP_MASK 0x1f
101 #define QIXIS_LBMAP_SHIFT 5
102 #define QIXIS_LBMAP_DFLTBANK 0x00
103 #define QIXIS_LBMAP_ALTBANK 0x20
104 #define QIXIS_LBMAP_SD 0x00
105 #define QIXIS_LBMAP_EMMC 0x00
106 #define QIXIS_LBMAP_SD_QSPI 0x00
107 #define QIXIS_LBMAP_QSPI 0x00
108 #define QIXIS_RCW_SRC_SD 0x40
109 #define QIXIS_RCW_SRC_EMMC 0x41
110 #define QIXIS_RCW_SRC_QSPI 0x62
111 #define QIXIS_RST_CTL_RESET 0x31
112 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
113 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
114 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
115 #define QIXIS_RST_FORCE_MEM 0x01
117 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
118 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
122 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
127 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
128 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
129 /* QIXIS Timing parameters*/
130 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
131 FTIM0_GPCM_TEADC(0x0e) | \
132 FTIM0_GPCM_TEAHC(0x0e))
133 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
134 FTIM1_GPCM_TRAD(0x3f))
135 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
136 FTIM2_GPCM_TCH(0xf) | \
137 FTIM2_GPCM_TWP(0x3E))
138 #define SYS_FPGA_CS_FTIM3 0x0
140 #if defined(CONFIG_TFABOOT) || \
141 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
142 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
143 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
144 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
145 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
146 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
147 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
148 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
149 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
150 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
151 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
152 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
153 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
154 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
155 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
156 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
157 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
158 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
160 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
161 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
162 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
163 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
164 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
165 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
166 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
167 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
168 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
171 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
173 #define I2C_MUX_CH_VOL_MONITOR 0xA
174 /* Voltage monitor on channel 2*/
175 #define I2C_VOL_MONITOR_ADDR 0x63
176 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
177 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
178 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
179 #define I2C_SVDD_MONITOR_ADDR 0x4F
181 /* The lowest and highest voltage allowed for LS1088ARDB */
182 #define VDD_MV_MIN 819
183 #define VDD_MV_MAX 1212
185 #define PWM_CHANNEL0 0x0
188 * I2C bus multiplexer
190 #define I2C_MUX_PCA_ADDR_PRI 0x77
191 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
192 #define I2C_RETIMER_ADDR 0x18
193 #define I2C_MUX_CH_DEFAULT 0x8
194 #define I2C_MUX_CH5 0xD
201 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
205 #define CONFIG_SYS_I2C_EEPROM_NXID
206 #define CONFIG_SYS_EEPROM_BUS_NUM 0
208 #define CONFIG_FSL_MEMAC
211 /* Initial environment variables */
212 #ifdef CONFIG_TFABOOT
213 #define QSPI_MC_INIT_CMD \
214 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
215 "sf read 0x80e00000 0xE00000 0x100000;" \
216 "env exists secureboot && " \
217 "sf read 0x80640000 0x640000 0x40000 && " \
218 "sf read 0x80680000 0x680000 0x40000 && " \
219 "esbc_validate 0x80640000 && " \
220 "esbc_validate 0x80680000 ;" \
221 "fsl_mc start mc 0x80a00000 0x80e00000\0"
222 #define SD_MC_INIT_CMD \
223 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
224 "mmc read 0x80e00000 0x7000 0x800;" \
225 "env exists secureboot && " \
226 "mmc read 0x80640000 0x3200 0x20 && " \
227 "mmc read 0x80680000 0x3400 0x20 && " \
228 "esbc_validate 0x80640000 && " \
229 "esbc_validate 0x80680000 ;" \
230 "fsl_mc start mc 0x80a00000 0x80e00000\0"
232 #if defined(CONFIG_QSPI_BOOT)
233 #define MC_INIT_CMD \
234 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
235 "sf read 0x80e00000 0xE00000 0x100000;" \
236 "env exists secureboot && " \
237 "sf read 0x80640000 0x640000 0x40000 && " \
238 "sf read 0x80680000 0x680000 0x40000 && " \
239 "esbc_validate 0x80640000 && " \
240 "esbc_validate 0x80680000 ;" \
241 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
242 "mcmemsize=0x70000000\0"
243 #elif defined(CONFIG_SD_BOOT)
244 #define MC_INIT_CMD \
245 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
246 "mmc read 0x80e00000 0x7000 0x800;" \
247 "env exists secureboot && " \
248 "mmc read 0x80640000 0x3200 0x20 && " \
249 "mmc read 0x80680000 0x3400 0x20 && " \
250 "esbc_validate 0x80640000 && " \
251 "esbc_validate 0x80680000 ;" \
252 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
253 "mcmemsize=0x70000000\0"
255 #endif /* CONFIG_TFABOOT */
257 #undef CONFIG_EXTRA_ENV_SETTINGS
258 #ifdef CONFIG_TFABOOT
259 #define CONFIG_EXTRA_ENV_SETTINGS \
260 "BOARD=ls1088ardb\0" \
261 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
262 "ramdisk_addr=0x800000\0" \
263 "ramdisk_size=0x2000000\0" \
264 "fdt_high=0xa0000000\0" \
265 "initrd_high=0xffffffffffffffff\0" \
266 "kernel_addr=0x1000000\0" \
267 "kernel_addr_sd=0x8000\0" \
268 "kernelhdr_addr_sd=0x3000\0" \
269 "kernel_start=0x580100000\0" \
270 "kernelheader_start=0x580600000\0" \
271 "scriptaddr=0x80000000\0" \
272 "scripthdraddr=0x80080000\0" \
273 "fdtheader_addr_r=0x80100000\0" \
274 "kernelheader_addr=0x600000\0" \
275 "kernelheader_addr_r=0x80200000\0" \
276 "kernel_addr_r=0x81000000\0" \
277 "kernelheader_size=0x40000\0" \
278 "fdt_addr_r=0x90000000\0" \
279 "load_addr=0xa0000000\0" \
280 "kernel_size=0x2800000\0" \
281 "kernel_size_sd=0x14000\0" \
282 "kernelhdr_size_sd=0x20\0" \
284 "mcmemsize=0x70000000\0" \
286 "boot_scripts=ls1088ardb_boot.scr\0" \
287 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
288 "scan_dev_for_boot_part=" \
289 "part list ${devtype} ${devnum} devplist; " \
290 "env exists devplist || setenv devplist 1; " \
291 "for distro_bootpart in ${devplist}; do " \
292 "if fstype ${devtype} " \
293 "${devnum}:${distro_bootpart} " \
294 "bootfstype; then " \
295 "run scan_dev_for_boot; " \
299 "load ${devtype} ${devnum}:${distro_bootpart} " \
300 "${scriptaddr} ${prefix}${script}; " \
301 "env exists secureboot && load ${devtype} " \
302 "${devnum}:${distro_bootpart} " \
303 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
304 "env exists secureboot " \
305 "&& esbc_validate ${scripthdraddr};" \
306 "source ${scriptaddr}\0" \
307 "installer=load mmc 0:2 $load_addr " \
308 "/flex_installer_arm64.itb; " \
309 "env exists mcinitcmd && run mcinitcmd && " \
310 "mmc read 0x80001000 0x6800 0x800;" \
311 "fsl_mc lazyapply dpl 0x80001000;" \
312 "bootm $load_addr#ls1088ardb\0" \
313 "qspi_bootcmd=echo Trying load from qspi..;" \
314 "sf probe && sf read $load_addr " \
315 "$kernel_addr $kernel_size ; env exists secureboot " \
316 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
317 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
318 "bootm $load_addr#$BOARD\0" \
319 "sd_bootcmd=echo Trying load from sd card..;" \
320 "mmcinfo; mmc read $load_addr " \
321 "$kernel_addr_sd $kernel_size_sd ;" \
322 "env exists secureboot && mmc read $kernelheader_addr_r "\
323 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
324 " && esbc_validate ${kernelheader_addr_r};" \
325 "bootm $load_addr#$BOARD\0"
327 #define CONFIG_EXTRA_ENV_SETTINGS \
328 "BOARD=ls1088ardb\0" \
329 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
330 "ramdisk_addr=0x800000\0" \
331 "ramdisk_size=0x2000000\0" \
332 "fdt_high=0xa0000000\0" \
333 "initrd_high=0xffffffffffffffff\0" \
334 "kernel_addr=0x1000000\0" \
335 "kernel_addr_sd=0x8000\0" \
336 "kernelhdr_addr_sd=0x3000\0" \
337 "kernel_start=0x580100000\0" \
338 "kernelheader_start=0x580800000\0" \
339 "scriptaddr=0x80000000\0" \
340 "scripthdraddr=0x80080000\0" \
341 "fdtheader_addr_r=0x80100000\0" \
342 "kernelheader_addr=0x600000\0" \
343 "kernelheader_addr_r=0x80200000\0" \
344 "kernel_addr_r=0x81000000\0" \
345 "kernelheader_size=0x40000\0" \
346 "fdt_addr_r=0x90000000\0" \
347 "load_addr=0xa0000000\0" \
348 "kernel_size=0x2800000\0" \
349 "kernel_size_sd=0x14000\0" \
350 "kernelhdr_size_sd=0x20\0" \
353 "boot_scripts=ls1088ardb_boot.scr\0" \
354 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
355 "scan_dev_for_boot_part=" \
356 "part list ${devtype} ${devnum} devplist; " \
357 "env exists devplist || setenv devplist 1; " \
358 "for distro_bootpart in ${devplist}; do " \
359 "if fstype ${devtype} " \
360 "${devnum}:${distro_bootpart} " \
361 "bootfstype; then " \
362 "run scan_dev_for_boot; " \
366 "load ${devtype} ${devnum}:${distro_bootpart} " \
367 "${scriptaddr} ${prefix}${script}; " \
368 "env exists secureboot && load ${devtype} " \
369 "${devnum}:${distro_bootpart} " \
370 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
371 "&& esbc_validate ${scripthdraddr};" \
372 "source ${scriptaddr}\0" \
373 "installer=load mmc 0:2 $load_addr " \
374 "/flex_installer_arm64.itb; " \
375 "env exists mcinitcmd && run mcinitcmd && " \
376 "mmc read 0x80001000 0x6800 0x800;" \
377 "fsl_mc lazyapply dpl 0x80001000;" \
378 "bootm $load_addr#ls1088ardb\0" \
379 "qspi_bootcmd=echo Trying load from qspi..;" \
380 "sf probe && sf read $load_addr " \
381 "$kernel_addr $kernel_size ; env exists secureboot " \
382 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
383 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
384 "bootm $load_addr#$BOARD\0" \
385 "sd_bootcmd=echo Trying load from sd card..;" \
386 "mmcinfo; mmc read $load_addr " \
387 "$kernel_addr_sd $kernel_size_sd ;" \
388 "env exists secureboot && mmc read $kernelheader_addr_r "\
389 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
390 " && esbc_validate ${kernelheader_addr_r};" \
391 "bootm $load_addr#$BOARD\0"
392 #endif /* CONFIG_TFABOOT */
394 #ifdef CONFIG_TFABOOT
395 #define QSPI_NOR_BOOTCOMMAND \
396 "sf read 0x80001000 0xd00000 0x100000;" \
397 "env exists mcinitcmd && env exists secureboot " \
398 " && sf read 0x806C0000 0x6C0000 0x100000 " \
399 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
400 "&& fsl_mc lazyapply dpl 0x80001000;" \
401 "run distro_bootcmd;run qspi_bootcmd;" \
402 "env exists secureboot && esbc_halt;"
403 #define SD_BOOTCOMMAND \
404 "env exists mcinitcmd && mmcinfo; " \
405 "mmc read 0x80001000 0x6800 0x800; " \
406 "env exists mcinitcmd && env exists secureboot " \
407 " && mmc read 0x806C0000 0x3600 0x20 " \
408 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
409 "&& fsl_mc lazyapply dpl 0x80001000;" \
410 "run distro_bootcmd;run sd_bootcmd;" \
411 "env exists secureboot && esbc_halt;"
413 #if defined(CONFIG_QSPI_BOOT)
414 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
416 /* Try to boot an on-SD kernel first, then do normal distro boot */
418 #endif /* CONFIG_TFABOOT */
420 /* MAC/PHY configuration */
421 #ifdef CONFIG_FSL_MC_ENET
422 #define AQ_PHY_ADDR1 0x00
423 #define AQR105_IRQ_MASK 0x00000004
425 #define QSGMII1_PORT1_PHY_ADDR 0x0c
426 #define QSGMII1_PORT2_PHY_ADDR 0x0d
427 #define QSGMII1_PORT3_PHY_ADDR 0x0e
428 #define QSGMII1_PORT4_PHY_ADDR 0x0f
429 #define QSGMII2_PORT1_PHY_ADDR 0x1c
430 #define QSGMII2_PORT2_PHY_ADDR 0x1d
431 #define QSGMII2_PORT3_PHY_ADDR 0x1e
432 #define QSGMII2_PORT4_PHY_ADDR 0x1f
438 #define BOOT_TARGET_DEVICES(func) \
441 func(SCSI, scsi, 0) \
443 #include <config_distro_bootcmd.h>
446 #include <asm/fsl_secure_boot.h>
448 #endif /* __LS1088A_RDB_H */