include/configs/ls1088aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020-2021 NXP
   4  */
   5
   6 #ifndef __LS1088A_QDS_H
   7 #define __LS1088A_QDS_H
   8
   9 #include "ls1088a_common.h"
  10
  11 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  12 #define SYS_NO_FLASH
  13 #endif
  14
  15 #define COUNTER_FREQUENCY_REAL          (get_board_sys_clk()/4)
  16
  17 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  18 #define SPD_EEPROM_ADDRESS              0x51
  19 #define CONFIG_SYS_SPD_BUS_NUM          0
  20
  21
  22 /*
  23  * IFC Definitions
  24  */
  25 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  26 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  27 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  28 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  29
  30 #define CONFIG_SYS_NOR0_CSPR                                    \
  31         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  32         CSPR_PORT_SIZE_16                                       | \
  33         CSPR_MSEL_NOR                                           | \
  34         CSPR_V)
  35 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  36         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  37         CSPR_PORT_SIZE_16                                       | \
  38         CSPR_MSEL_NOR                                           | \
  39         CSPR_V)
  40 #define CONFIG_SYS_NOR1_CSPR                                    \
  41         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  42         CSPR_PORT_SIZE_16                                       | \
  43         CSPR_MSEL_NOR                                           | \
  44         CSPR_V)
  45 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  46         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  47         CSPR_PORT_SIZE_16                                       | \
  48         CSPR_MSEL_NOR                                           | \
  49         CSPR_V)
  50 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  51 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  52                                 FTIM0_NOR_TEADC(0x5) | \
  53                                 FTIM0_NOR_TAVDS(0x6) | \
  54                                 FTIM0_NOR_TEAHC(0x5))
  55 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  56                                 FTIM1_NOR_TRAD_NOR(0x1a) | \
  57                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  58 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x8) | \
  59                                 FTIM2_NOR_TCH(0x8) | \
  60                                 FTIM2_NOR_TWPH(0xe) | \
  61                                 FTIM2_NOR_TWP(0x1c))
  62 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  63 #define CONFIG_SYS_IFC_CCR      0x01000000
  64
  65 #ifndef SYS_NO_FLASH
  66 #define CONFIG_SYS_FLASH_QUIET_TEST
  67 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  68
  69 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  70 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  71 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  72
  73 #define CONFIG_SYS_FLASH_EMPTY_INFO
  74 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  75                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  76 #endif
  77 #endif
  78
  79 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  80 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  81
  82 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  83 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  84                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  85                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  86                                 | CSPR_V)
  87 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  88
  89 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  90                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  91                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  92                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  93                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  94                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  95                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
  96
  97 /* ONFI NAND Flash mode0 Timing Params */
  98 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
  99                                         FTIM0_NAND_TWP(0x18)   | \
 100                                         FTIM0_NAND_TWCHT(0x07) | \
 101                                         FTIM0_NAND_TWH(0x0a))
 102 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 103                                         FTIM1_NAND_TWBE(0x39)  | \
 104                                         FTIM1_NAND_TRR(0x0e)   | \
 105                                         FTIM1_NAND_TRP(0x18))
 106 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 107                                         FTIM2_NAND_TREH(0x0a) | \
 108                                         FTIM2_NAND_TWHRE(0x1e))
 109 #define CONFIG_SYS_NAND_FTIM3           0x0
 110
 111 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 112 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 113 #define CONFIG_MTD_NAND_VERIFY_WRITE
 114
 115 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 116 #define QIXIS_LBMAP_SWITCH              6
 117 #define QIXIS_QMAP_MASK                 0xe0
 118 #define QIXIS_QMAP_SHIFT                5
 119 #define QIXIS_LBMAP_MASK                0x0f
 120 #define QIXIS_LBMAP_SHIFT               0
 121 #define QIXIS_LBMAP_DFLTBANK            0x0e
 122 #define QIXIS_LBMAP_ALTBANK             0x2e
 123 #define QIXIS_LBMAP_SD                  0x00
 124 #define QIXIS_LBMAP_EMMC                0x00
 125 #define QIXIS_LBMAP_IFC                 0x00
 126 #define QIXIS_LBMAP_SD_QSPI             0x0e
 127 #define QIXIS_LBMAP_QSPI                0x0e
 128 #define QIXIS_RCW_SRC_IFC               0x25
 129 #define QIXIS_RCW_SRC_SD                0x40
 130 #define QIXIS_RCW_SRC_EMMC              0x41
 131 #define QIXIS_RCW_SRC_QSPI              0x62
 132 #define QIXIS_RST_CTL_RESET             0x41
 133 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 134 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 135 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 136 #define QIXIS_RST_FORCE_MEM             0x01
 137 #define QIXIS_STAT_PRES1                0xb
 138 #define QIXIS_SDID_MASK                 0x07
 139 #define QIXIS_ESDHC_NO_ADAPTER          0x7
 140
 141 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 142 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 143                                         | CSPR_PORT_SIZE_8 \
 144                                         | CSPR_MSEL_GPCM \
 145                                         | CSPR_V)
 146 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 147                                         | CSPR_PORT_SIZE_8 \
 148                                         | CSPR_MSEL_GPCM \
 149                                         | CSPR_V)
 150
 151 #define SYS_FPGA_AMASK          IFC_AMASK(64 * 1024)
 152 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 153 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 154 #else
 155 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(12)
 156 #endif
 157 /* QIXIS Timing parameters*/
 158 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 159                                         FTIM0_GPCM_TEADC(0x0e) | \
 160                                         FTIM0_GPCM_TEAHC(0x0e))
 161 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 162                                         FTIM1_GPCM_TRAD(0x3f))
 163 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 164                                         FTIM2_GPCM_TCH(0xf) | \
 165                                         FTIM2_GPCM_TWP(0x3E))
 166 #define SYS_FPGA_CS_FTIM3       0x0
 167
 168 #ifdef CONFIG_TFABOOT
 169 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 170 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 171 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 172 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 173 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 174 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 175 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 176 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 177 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 178 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 179 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 180 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 181 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 182 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 183 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 184 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 185 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 186 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 187 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 188 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 189 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 190 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 191 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 192 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 193 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 194 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 195 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 196 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 197 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 198 #define CONFIG_SYS_CSPR3_FINAL          SYS_FPGA_CSPR_FINAL
 199 #define CONFIG_SYS_AMASK3               SYS_FPGA_AMASK
 200 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 201 #define CONFIG_SYS_CS3_FTIM0            SYS_FPGA_CS_FTIM0
 202 #define CONFIG_SYS_CS3_FTIM1            SYS_FPGA_CS_FTIM1
 203 #define CONFIG_SYS_CS3_FTIM2            SYS_FPGA_CS_FTIM2
 204 #define CONFIG_SYS_CS3_FTIM3            SYS_FPGA_CS_FTIM3
 205 #else
 206 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 207 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 208 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 209 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 210 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 211 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 212 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 213 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 214 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 215 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 216 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 217 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 218 #define CONFIG_SYS_AMASK2               SYS_FPGA_AMASK
 219 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 220 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 221 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 222 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 223 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 224 #else
 225 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 226 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 227 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 228 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 229 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 230 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 231 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 232 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 233 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 234 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 235 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 236 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 237 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 238 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 239 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 240 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 241 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 242 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 243 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 244 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 245 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 246 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 247 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 248 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 249 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 250 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 251 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 252 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 253 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 254 #define CONFIG_SYS_CSPR3_FINAL          SYS_FPGA_CSPR_FINAL
 255 #define CONFIG_SYS_AMASK3               SYS_FPGA_AMASK
 256 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 257 #define CONFIG_SYS_CS3_FTIM0            SYS_FPGA_CS_FTIM0
 258 #define CONFIG_SYS_CS3_FTIM1            SYS_FPGA_CS_FTIM1
 259 #define CONFIG_SYS_CS3_FTIM2            SYS_FPGA_CS_FTIM2
 260 #define CONFIG_SYS_CS3_FTIM3            SYS_FPGA_CS_FTIM3
 261 #endif
 262 #endif
 263
 264 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 265
 266 /*
 267  * I2C bus multiplexer
 268  */
 269 #define I2C_MUX_PCA_ADDR_PRI            0x77
 270 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 271 #define I2C_RETIMER_ADDR                0x18
 272 #define I2C_RETIMER_ADDR2               0x19
 273 #define I2C_MUX_CH_DEFAULT              0x8
 274 #define I2C_MUX_CH5                     0xD
 275
 276 #define I2C_MUX_CH_VOL_MONITOR          0xA
 277
 278 /* Voltage monitor on channel 2*/
 279 #define I2C_VOL_MONITOR_ADDR           0x63
 280 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 281 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 282 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 283 #define I2C_SVDD_MONITOR_ADDR           0x4F
 284
 285 /* The lowest and highest voltage allowed for LS1088AQDS */
 286 #define VDD_MV_MIN                      819
 287 #define VDD_MV_MAX                      1212
 288
 289 #define PWM_CHANNEL0                    0x0
 290
 291 /*
 292 * RTC configuration
 293 */
 294 #define RTC
 295 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 296
 297 /* EEPROM */
 298 #define CONFIG_SYS_I2C_EEPROM_NXID
 299 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 300
 301 #ifdef CONFIG_FSL_DSPI
 302 #if !defined(CONFIG_TFABOOT) && \
 303         !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 304 #endif
 305 #endif
 306
 307 #define CONFIG_FSL_MEMAC
 308
 309 /*  MMC  */
 310 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
 311         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
 312
 313 #define COMMON_ENV \
 314         "kernelheader_addr_r=0x80200000\0"      \
 315         "fdtheader_addr_r=0x80100000\0"         \
 316         "kernel_addr_r=0x81000000\0"            \
 317         "fdt_addr_r=0x90000000\0"               \
 318         "load_addr=0xa0000000\0"
 319
 320 /* Initial environment variables */
 321 #ifdef CONFIG_NXP_ESBC
 322 #undef CONFIG_EXTRA_ENV_SETTINGS
 323 #define CONFIG_EXTRA_ENV_SETTINGS               \
 324         COMMON_ENV                              \
 325         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 326         "loadaddr=0x90100000\0"                 \
 327         "kernel_addr=0x100000\0"                \
 328         "ramdisk_addr=0x800000\0"               \
 329         "ramdisk_size=0x2000000\0"              \
 330         "fdt_high=0xa0000000\0"                 \
 331         "initrd_high=0xffffffffffffffff\0"      \
 332         "kernel_start=0x1000000\0"              \
 333         "kernel_load=0xa0000000\0"              \
 334         "kernel_size=0x2800000\0"               \
 335         "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;"  \
 336         "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
 337         "sf read 0xa0e00000 0xe00000 0x100000;" \
 338         "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;"  \
 339         "fsl_mc start mc 0xa0a00000 0xa0e00000\0"                       \
 340         "mcmemsize=0x70000000 \0"
 341 #else /* if !(CONFIG_NXP_ESBC) */
 342 #ifdef CONFIG_TFABOOT
 343 #define QSPI_MC_INIT_CMD                                \
 344         "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"    \
 345         "sf read 0x80e00000 0xE00000 0x100000;" \
 346         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 347 #define SD_MC_INIT_CMD                          \
 348         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 349         "mmc read 0x80e00000 0x7000 0x800;" \
 350         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 351 #define IFC_MC_INIT_CMD                         \
 352         "fsl_mc start mc 0x580A00000 0x580E00000\0"
 353
 354 #undef CONFIG_EXTRA_ENV_SETTINGS
 355 #define CONFIG_EXTRA_ENV_SETTINGS               \
 356         COMMON_ENV                              \
 357         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 358         "loadaddr=0x90100000\0"                 \
 359         "kernel_addr=0x100000\0"                \
 360         "kernel_addr_sd=0x800\0"                \
 361         "ramdisk_addr=0x800000\0"               \
 362         "ramdisk_size=0x2000000\0"              \
 363         "fdt_high=0xa0000000\0"                 \
 364         "initrd_high=0xffffffffffffffff\0"      \
 365         "kernel_start=0x1000000\0"              \
 366         "kernel_start_sd=0x8000\0"              \
 367         "kernel_load=0xa0000000\0"              \
 368         "kernel_size=0x2800000\0"               \
 369         "kernel_size_sd=0x14000\0"               \
 370         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 371         "sf read 0x80e00000 0xE00000 0x100000;" \
 372         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 373         "mcmemsize=0x70000000 \0"               \
 374         "BOARD=ls1088aqds\0" \
 375         "scriptaddr=0x80000000\0"               \
 376         "scripthdraddr=0x80080000\0"            \
 377         BOOTENV                                 \
 378         "boot_scripts=ls1088aqds_boot.scr\0"    \
 379         "boot_script_hdr=hdr_ls1088aqds_bs.out\0"       \
 380         "scan_dev_for_boot_part="               \
 381                 "part list ${devtype} ${devnum} devplist; "     \
 382                 "env exists devplist || setenv devplist 1; "    \
 383                 "for distro_bootpart in ${devplist}; do "       \
 384                         "if fstype ${devtype} "                 \
 385                                 "${devnum}:${distro_bootpart} " \
 386                                 "bootfstype; then "             \
 387                                 "run scan_dev_for_boot; "       \
 388                         "fi; "                                  \
 389                 "done\0"                                        \
 390         "boot_a_script="                                        \
 391                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 392                 "${scriptaddr} ${prefix}${script}; "            \
 393         "env exists secureboot && load ${devtype} "             \
 394                 "${devnum}:${distro_bootpart} "                 \
 395                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 396                 "env exists secureboot "                        \
 397                 "&& esbc_validate ${scripthdraddr};"            \
 398                 "source ${scriptaddr}\0"                        \
 399         "qspi_bootcmd=echo Trying load from qspi..; " \
 400                 "sf probe 0:0; " \
 401                 "sf read 0x80001000 0xd00000 0x100000; " \
 402                 "fsl_mc lazyapply dpl 0x80001000 && " \
 403                 "sf read $kernel_load $kernel_start " \
 404                 "$kernel_size && bootm $kernel_load#$BOARD\0" \
 405         "sd_bootcmd=echo Trying load from sd card..; " \
 406                 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
 407                 "fsl_mc lazyapply dpl 0x80001000 && " \
 408                 "mmc read $kernel_load $kernel_start_sd " \
 409                 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
 410         "nor_bootcmd=echo Trying load from nor..; " \
 411                 "fsl_mc lazyapply dpl 0x580d00000 && " \
 412                 "cp.b $kernel_start $kernel_load " \
 413                 "$kernel_size && bootm $kernel_load#$BOARD\0"
 414 #else
 415 #if defined(CONFIG_QSPI_BOOT)
 416 #undef CONFIG_EXTRA_ENV_SETTINGS
 417 #define CONFIG_EXTRA_ENV_SETTINGS               \
 418         COMMON_ENV                              \
 419         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 420         "loadaddr=0x90100000\0"                 \
 421         "kernel_addr=0x100000\0"                \
 422         "ramdisk_addr=0x800000\0"               \
 423         "ramdisk_size=0x2000000\0"              \
 424         "fdt_high=0xa0000000\0"                 \
 425         "initrd_high=0xffffffffffffffff\0"      \
 426         "kernel_start=0x1000000\0"              \
 427         "kernel_load=0xa0000000\0"              \
 428         "kernel_size=0x2800000\0"               \
 429         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 430         "sf read 0x80e00000 0xE00000 0x100000;" \
 431         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 432         "mcmemsize=0x70000000 \0"
 433 #elif defined(CONFIG_SD_BOOT)
 434 #undef CONFIG_EXTRA_ENV_SETTINGS
 435 #define CONFIG_EXTRA_ENV_SETTINGS               \
 436         COMMON_ENV                              \
 437         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 438         "loadaddr=0x90100000\0"                 \
 439         "kernel_addr=0x800\0"                \
 440         "ramdisk_addr=0x800000\0"               \
 441         "ramdisk_size=0x2000000\0"              \
 442         "fdt_high=0xa0000000\0"                 \
 443         "initrd_high=0xffffffffffffffff\0"      \
 444         "kernel_start=0x8000\0"              \
 445         "kernel_load=0xa0000000\0"              \
 446         "kernel_size=0x14000\0"               \
 447         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 448         "mmc read 0x80e00000 0x7000 0x800;" \
 449         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 450         "mcmemsize=0x70000000 \0"
 451 #else   /* NOR BOOT */
 452 #undef CONFIG_EXTRA_ENV_SETTINGS
 453 #define CONFIG_EXTRA_ENV_SETTINGS               \
 454         COMMON_ENV                              \
 455         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 456         "loadaddr=0x90100000\0"                 \
 457         "kernel_addr=0x100000\0"                \
 458         "ramdisk_addr=0x800000\0"               \
 459         "ramdisk_size=0x2000000\0"              \
 460         "fdt_high=0xa0000000\0"                 \
 461         "initrd_high=0xffffffffffffffff\0"      \
 462         "kernel_start=0x1000000\0"              \
 463         "kernel_load=0xa0000000\0"              \
 464         "kernel_size=0x2800000\0"               \
 465         "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0"   \
 466         "mcmemsize=0x70000000 \0"
 467 #endif
 468 #endif /* CONFIG_TFABOOT */
 469 #endif /* CONFIG_NXP_ESBC */
 470
 471 #ifdef CONFIG_TFABOOT
 472 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 473                            "env exists secureboot && esbc_halt;;"
 474 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 475                            "env exists secureboot && esbc_halt;;"
 476 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 477                            "env exists secureboot && esbc_halt;;"
 478 #endif
 479
 480 #ifdef CONFIG_FSL_MC_ENET
 481 #define CONFIG_FSL_MEMAC
 482 #define RGMII_PHY1_ADDR         0x1
 483 #define RGMII_PHY2_ADDR         0x2
 484 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 485 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 486 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 487 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 488
 489 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 490 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 491 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 492 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 493 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 494 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 495 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 496 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 497 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 498 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 499 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 500 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 501 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 502 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 503 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 504 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 505
 506 #endif
 507
 508 #define BOOT_TARGET_DEVICES(func) \
 509         func(USB, usb, 0) \
 510         func(MMC, mmc, 0) \
 511         func(SCSI, scsi, 0) \
 512         func(DHCP, dhcp, na)
 513 #include <config_distro_bootcmd.h>
 514
 515 #include <asm/fsl_secure_boot.h>
 516
 517 #endif /* __LS1088A_QDS_H */