include/configs/ls1088aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020-2021 NXP
   4  */
   5
   6 #ifndef __LS1088A_QDS_H
   7 #define __LS1088A_QDS_H
   8
   9 #include "ls1088a_common.h"
  10
  11
  12 #ifndef __ASSEMBLY__
  13 unsigned long get_board_sys_clk(void);
  14 #endif
  15
  16 #ifdef CONFIG_TFABOOT
  17 #define CONFIG_MISC_INIT_R
  18 #endif
  19
  20 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  21 #define CONFIG_QIXIS_I2C_ACCESS
  22 #define SYS_NO_FLASH
  23
  24 #define CONFIG_SYS_CLK_FREQ             100000000
  25 #else
  26 #define CONFIG_QIXIS_I2C_ACCESS
  27 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  28 #endif
  29
  30 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  31 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  32
  33 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  34
  35 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  36 #define SPD_EEPROM_ADDRESS              0x51
  37 #define CONFIG_SYS_SPD_BUS_NUM          0
  38
  39
  40 /*
  41  * IFC Definitions
  42  */
  43 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  44 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  45 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  46 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  47
  48 #define CONFIG_SYS_NOR0_CSPR                                    \
  49         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  50         CSPR_PORT_SIZE_16                                       | \
  51         CSPR_MSEL_NOR                                           | \
  52         CSPR_V)
  53 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  54         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  55         CSPR_PORT_SIZE_16                                       | \
  56         CSPR_MSEL_NOR                                           | \
  57         CSPR_V)
  58 #define CONFIG_SYS_NOR1_CSPR                                    \
  59         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  60         CSPR_PORT_SIZE_16                                       | \
  61         CSPR_MSEL_NOR                                           | \
  62         CSPR_V)
  63 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  64         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  65         CSPR_PORT_SIZE_16                                       | \
  66         CSPR_MSEL_NOR                                           | \
  67         CSPR_V)
  68 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  69 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  70                                 FTIM0_NOR_TEADC(0x5) | \
  71                                 FTIM0_NOR_TAVDS(0x6) | \
  72                                 FTIM0_NOR_TEAHC(0x5))
  73 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  74                                 FTIM1_NOR_TRAD_NOR(0x1a) | \
  75                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  76 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x8) | \
  77                                 FTIM2_NOR_TCH(0x8) | \
  78                                 FTIM2_NOR_TWPH(0xe) | \
  79                                 FTIM2_NOR_TWP(0x1c))
  80 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  81 #define CONFIG_SYS_IFC_CCR      0x01000000
  82
  83 #ifndef SYS_NO_FLASH
  84 #define CONFIG_SYS_FLASH_QUIET_TEST
  85 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  86
  87 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
  88 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  89 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  90 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  91
  92 #define CONFIG_SYS_FLASH_EMPTY_INFO
  93 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  94                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  95 #endif
  96 #endif
  97
  98 #define CONFIG_NAND_FSL_IFC
  99 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 100 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 101
 102 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 103 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 104                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 105                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 106                                 | CSPR_V)
 107 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 108
 109 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 110                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 111                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 112                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 113                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 114                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 115                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 116
 117 #define CONFIG_SYS_NAND_ONFI_DETECTION
 118
 119 /* ONFI NAND Flash mode0 Timing Params */
 120 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 121                                         FTIM0_NAND_TWP(0x18)   | \
 122                                         FTIM0_NAND_TWCHT(0x07) | \
 123                                         FTIM0_NAND_TWH(0x0a))
 124 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 125                                         FTIM1_NAND_TWBE(0x39)  | \
 126                                         FTIM1_NAND_TRR(0x0e)   | \
 127                                         FTIM1_NAND_TRP(0x18))
 128 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 129                                         FTIM2_NAND_TREH(0x0a) | \
 130                                         FTIM2_NAND_TWHRE(0x1e))
 131 #define CONFIG_SYS_NAND_FTIM3           0x0
 132
 133 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 134 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 135 #define CONFIG_MTD_NAND_VERIFY_WRITE
 136
 137 #define CONFIG_FSL_QIXIS
 138 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 139 #define QIXIS_LBMAP_SWITCH              6
 140 #define QIXIS_QMAP_MASK                 0xe0
 141 #define QIXIS_QMAP_SHIFT                5
 142 #define QIXIS_LBMAP_MASK                0x0f
 143 #define QIXIS_LBMAP_SHIFT               0
 144 #define QIXIS_LBMAP_DFLTBANK            0x0e
 145 #define QIXIS_LBMAP_ALTBANK             0x2e
 146 #define QIXIS_LBMAP_SD                  0x00
 147 #define QIXIS_LBMAP_EMMC                0x00
 148 #define QIXIS_LBMAP_IFC                 0x00
 149 #define QIXIS_LBMAP_SD_QSPI             0x0e
 150 #define QIXIS_LBMAP_QSPI                0x0e
 151 #define QIXIS_RCW_SRC_IFC               0x25
 152 #define QIXIS_RCW_SRC_SD                0x40
 153 #define QIXIS_RCW_SRC_EMMC              0x41
 154 #define QIXIS_RCW_SRC_QSPI              0x62
 155 #define QIXIS_RST_CTL_RESET             0x41
 156 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 157 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 158 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 159 #define QIXIS_RST_FORCE_MEM             0x01
 160 #define QIXIS_STAT_PRES1                0xb
 161 #define QIXIS_SDID_MASK                 0x07
 162 #define QIXIS_ESDHC_NO_ADAPTER          0x7
 163
 164 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 165 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 166                                         | CSPR_PORT_SIZE_8 \
 167                                         | CSPR_MSEL_GPCM \
 168                                         | CSPR_V)
 169 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 170                                         | CSPR_PORT_SIZE_8 \
 171                                         | CSPR_MSEL_GPCM \
 172                                         | CSPR_V)
 173
 174 #define SYS_FPGA_AMASK          IFC_AMASK(64 * 1024)
 175 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 176 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 177 #else
 178 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(12)
 179 #endif
 180 /* QIXIS Timing parameters*/
 181 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 182                                         FTIM0_GPCM_TEADC(0x0e) | \
 183                                         FTIM0_GPCM_TEAHC(0x0e))
 184 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 185                                         FTIM1_GPCM_TRAD(0x3f))
 186 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 187                                         FTIM2_GPCM_TCH(0xf) | \
 188                                         FTIM2_GPCM_TWP(0x3E))
 189 #define SYS_FPGA_CS_FTIM3       0x0
 190
 191 #ifdef CONFIG_TFABOOT
 192 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 193 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 194 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 195 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 196 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 197 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 198 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 199 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 200 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 201 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 202 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 203 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 204 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 205 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 206 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 207 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 208 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 209 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 210 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 211 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 212 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 213 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 214 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 215 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 216 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 217 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 218 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 219 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 220 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 221 #define CONFIG_SYS_CSPR3_FINAL          SYS_FPGA_CSPR_FINAL
 222 #define CONFIG_SYS_AMASK3               SYS_FPGA_AMASK
 223 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 224 #define CONFIG_SYS_CS3_FTIM0            SYS_FPGA_CS_FTIM0
 225 #define CONFIG_SYS_CS3_FTIM1            SYS_FPGA_CS_FTIM1
 226 #define CONFIG_SYS_CS3_FTIM2            SYS_FPGA_CS_FTIM2
 227 #define CONFIG_SYS_CS3_FTIM3            SYS_FPGA_CS_FTIM3
 228 #else
 229 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 230 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 231 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 232 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 233 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 234 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 235 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 236 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 237 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 238 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 239 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 240 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 241 #define CONFIG_SYS_AMASK2               SYS_FPGA_AMASK
 242 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 243 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 244 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 245 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 246 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 247 #else
 248 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 249 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 250 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 251 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 252 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 253 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 254 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 255 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 256 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 257 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 258 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 259 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 260 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 261 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 262 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 263 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 264 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 265 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 266 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 267 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 268 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 269 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 270 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 271 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 272 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 273 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 274 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 275 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 276 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 277 #define CONFIG_SYS_CSPR3_FINAL          SYS_FPGA_CSPR_FINAL
 278 #define CONFIG_SYS_AMASK3               SYS_FPGA_AMASK
 279 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 280 #define CONFIG_SYS_CS3_FTIM0            SYS_FPGA_CS_FTIM0
 281 #define CONFIG_SYS_CS3_FTIM1            SYS_FPGA_CS_FTIM1
 282 #define CONFIG_SYS_CS3_FTIM2            SYS_FPGA_CS_FTIM2
 283 #define CONFIG_SYS_CS3_FTIM3            SYS_FPGA_CS_FTIM3
 284 #endif
 285 #endif
 286
 287 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 288
 289 /*
 290  * I2C bus multiplexer
 291  */
 292 #define I2C_MUX_PCA_ADDR_PRI            0x77
 293 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 294 #define I2C_RETIMER_ADDR                0x18
 295 #define I2C_RETIMER_ADDR2               0x19
 296 #define I2C_MUX_CH_DEFAULT              0x8
 297 #define I2C_MUX_CH5                     0xD
 298
 299 #define I2C_MUX_CH_VOL_MONITOR          0xA
 300
 301 /* Voltage monitor on channel 2*/
 302 #define I2C_VOL_MONITOR_ADDR           0x63
 303 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 304 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 305 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 306 #define I2C_SVDD_MONITOR_ADDR           0x4F
 307
 308 #define CONFIG_VID_FLS_ENV              "ls1088aqds_vdd_mv"
 309 #define CONFIG_VID
 310
 311 /* The lowest and highest voltage allowed for LS1088AQDS */
 312 #define VDD_MV_MIN                      819
 313 #define VDD_MV_MAX                      1212
 314
 315 #define CONFIG_VOL_MONITOR_LTC3882_SET
 316 #define CONFIG_VOL_MONITOR_LTC3882_READ
 317
 318 #define PWM_CHANNEL0                    0x0
 319
 320 /*
 321 * RTC configuration
 322 */
 323 #define RTC
 324 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 325
 326 /* EEPROM */
 327 #define CONFIG_SYS_I2C_EEPROM_NXID
 328 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 329
 330 #ifdef CONFIG_FSL_DSPI
 331 #define CONFIG_SPI_FLASH_STMICRO
 332 #define CONFIG_SPI_FLASH_SST
 333 #define CONFIG_SPI_FLASH_EON
 334 #if !defined(CONFIG_TFABOOT) && \
 335         !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 336 #endif
 337 #endif
 338
 339 #ifdef CONFIG_SPL_BUILD
 340 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 341 #else
 342 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 343 #endif
 344
 345 #define CONFIG_FSL_MEMAC
 346
 347 /*  MMC  */
 348 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
 349         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
 350
 351 #define COMMON_ENV \
 352         "kernelheader_addr_r=0x80200000\0"      \
 353         "fdtheader_addr_r=0x80100000\0"         \
 354         "kernel_addr_r=0x81000000\0"            \
 355         "fdt_addr_r=0x90000000\0"               \
 356         "load_addr=0xa0000000\0"
 357
 358 /* Initial environment variables */
 359 #ifdef CONFIG_NXP_ESBC
 360 #undef CONFIG_EXTRA_ENV_SETTINGS
 361 #define CONFIG_EXTRA_ENV_SETTINGS               \
 362         COMMON_ENV                              \
 363         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 364         "loadaddr=0x90100000\0"                 \
 365         "kernel_addr=0x100000\0"                \
 366         "ramdisk_addr=0x800000\0"               \
 367         "ramdisk_size=0x2000000\0"              \
 368         "fdt_high=0xa0000000\0"                 \
 369         "initrd_high=0xffffffffffffffff\0"      \
 370         "kernel_start=0x1000000\0"              \
 371         "kernel_load=0xa0000000\0"              \
 372         "kernel_size=0x2800000\0"               \
 373         "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;"  \
 374         "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
 375         "sf read 0xa0e00000 0xe00000 0x100000;" \
 376         "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;"  \
 377         "fsl_mc start mc 0xa0a00000 0xa0e00000\0"                       \
 378         "mcmemsize=0x70000000 \0"
 379 #else /* if !(CONFIG_NXP_ESBC) */
 380 #ifdef CONFIG_TFABOOT
 381 #define QSPI_MC_INIT_CMD                                \
 382         "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"    \
 383         "sf read 0x80e00000 0xE00000 0x100000;" \
 384         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 385 #define SD_MC_INIT_CMD                          \
 386         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 387         "mmc read 0x80e00000 0x7000 0x800;" \
 388         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 389 #define IFC_MC_INIT_CMD                         \
 390         "fsl_mc start mc 0x580A00000 0x580E00000\0"
 391
 392 #undef CONFIG_EXTRA_ENV_SETTINGS
 393 #define CONFIG_EXTRA_ENV_SETTINGS               \
 394         COMMON_ENV                              \
 395         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 396         "loadaddr=0x90100000\0"                 \
 397         "kernel_addr=0x100000\0"                \
 398         "kernel_addr_sd=0x800\0"                \
 399         "ramdisk_addr=0x800000\0"               \
 400         "ramdisk_size=0x2000000\0"              \
 401         "fdt_high=0xa0000000\0"                 \
 402         "initrd_high=0xffffffffffffffff\0"      \
 403         "kernel_start=0x1000000\0"              \
 404         "kernel_start_sd=0x8000\0"              \
 405         "kernel_load=0xa0000000\0"              \
 406         "kernel_size=0x2800000\0"               \
 407         "kernel_size_sd=0x14000\0"               \
 408         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 409         "sf read 0x80e00000 0xE00000 0x100000;" \
 410         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 411         "mcmemsize=0x70000000 \0"               \
 412         "BOARD=ls1088aqds\0" \
 413         "scriptaddr=0x80000000\0"               \
 414         "scripthdraddr=0x80080000\0"            \
 415         BOOTENV                                 \
 416         "boot_scripts=ls1088aqds_boot.scr\0"    \
 417         "boot_script_hdr=hdr_ls1088aqds_bs.out\0"       \
 418         "scan_dev_for_boot_part="               \
 419                 "part list ${devtype} ${devnum} devplist; "     \
 420                 "env exists devplist || setenv devplist 1; "    \
 421                 "for distro_bootpart in ${devplist}; do "       \
 422                         "if fstype ${devtype} "                 \
 423                                 "${devnum}:${distro_bootpart} " \
 424                                 "bootfstype; then "             \
 425                                 "run scan_dev_for_boot; "       \
 426                         "fi; "                                  \
 427                 "done\0"                                        \
 428         "boot_a_script="                                        \
 429                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 430                 "${scriptaddr} ${prefix}${script}; "            \
 431         "env exists secureboot && load ${devtype} "             \
 432                 "${devnum}:${distro_bootpart} "                 \
 433                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 434                 "env exists secureboot "                        \
 435                 "&& esbc_validate ${scripthdraddr};"            \
 436                 "source ${scriptaddr}\0"                        \
 437         "qspi_bootcmd=echo Trying load from qspi..; " \
 438                 "sf probe 0:0; " \
 439                 "sf read 0x80001000 0xd00000 0x100000; " \
 440                 "fsl_mc lazyapply dpl 0x80001000 && " \
 441                 "sf read $kernel_load $kernel_start " \
 442                 "$kernel_size && bootm $kernel_load#$BOARD\0" \
 443         "sd_bootcmd=echo Trying load from sd card..; " \
 444                 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
 445                 "fsl_mc lazyapply dpl 0x80001000 && " \
 446                 "mmc read $kernel_load $kernel_start_sd " \
 447                 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
 448         "nor_bootcmd=echo Trying load from nor..; " \
 449                 "fsl_mc lazyapply dpl 0x580d00000 && " \
 450                 "cp.b $kernel_start $kernel_load " \
 451                 "$kernel_size && bootm $kernel_load#$BOARD\0"
 452 #else
 453 #if defined(CONFIG_QSPI_BOOT)
 454 #undef CONFIG_EXTRA_ENV_SETTINGS
 455 #define CONFIG_EXTRA_ENV_SETTINGS               \
 456         COMMON_ENV                              \
 457         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 458         "loadaddr=0x90100000\0"                 \
 459         "kernel_addr=0x100000\0"                \
 460         "ramdisk_addr=0x800000\0"               \
 461         "ramdisk_size=0x2000000\0"              \
 462         "fdt_high=0xa0000000\0"                 \
 463         "initrd_high=0xffffffffffffffff\0"      \
 464         "kernel_start=0x1000000\0"              \
 465         "kernel_load=0xa0000000\0"              \
 466         "kernel_size=0x2800000\0"               \
 467         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 468         "sf read 0x80e00000 0xE00000 0x100000;" \
 469         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 470         "mcmemsize=0x70000000 \0"
 471 #elif defined(CONFIG_SD_BOOT)
 472 #undef CONFIG_EXTRA_ENV_SETTINGS
 473 #define CONFIG_EXTRA_ENV_SETTINGS               \
 474         COMMON_ENV                              \
 475         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 476         "loadaddr=0x90100000\0"                 \
 477         "kernel_addr=0x800\0"                \
 478         "ramdisk_addr=0x800000\0"               \
 479         "ramdisk_size=0x2000000\0"              \
 480         "fdt_high=0xa0000000\0"                 \
 481         "initrd_high=0xffffffffffffffff\0"      \
 482         "kernel_start=0x8000\0"              \
 483         "kernel_load=0xa0000000\0"              \
 484         "kernel_size=0x14000\0"               \
 485         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 486         "mmc read 0x80e00000 0x7000 0x800;" \
 487         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 488         "mcmemsize=0x70000000 \0"
 489 #else   /* NOR BOOT */
 490 #undef CONFIG_EXTRA_ENV_SETTINGS
 491 #define CONFIG_EXTRA_ENV_SETTINGS               \
 492         COMMON_ENV                              \
 493         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 494         "loadaddr=0x90100000\0"                 \
 495         "kernel_addr=0x100000\0"                \
 496         "ramdisk_addr=0x800000\0"               \
 497         "ramdisk_size=0x2000000\0"              \
 498         "fdt_high=0xa0000000\0"                 \
 499         "initrd_high=0xffffffffffffffff\0"      \
 500         "kernel_start=0x1000000\0"              \
 501         "kernel_load=0xa0000000\0"              \
 502         "kernel_size=0x2800000\0"               \
 503         "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0"   \
 504         "mcmemsize=0x70000000 \0"
 505 #endif
 506 #endif /* CONFIG_TFABOOT */
 507 #endif /* CONFIG_NXP_ESBC */
 508
 509 #ifdef CONFIG_TFABOOT
 510 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 511                            "env exists secureboot && esbc_halt;;"
 512 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 513                            "env exists secureboot && esbc_halt;;"
 514 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 515                            "env exists secureboot && esbc_halt;;"
 516 #endif
 517
 518 #ifdef CONFIG_FSL_MC_ENET
 519 #define CONFIG_FSL_MEMAC
 520 #define RGMII_PHY1_ADDR         0x1
 521 #define RGMII_PHY2_ADDR         0x2
 522 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 523 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 524 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 525 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 526
 527 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 528 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 529 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 530 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 531 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 532 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 533 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 534 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 535 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 536 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 537 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 538 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 539 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 540 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 541 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 542 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 543
 544 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 545 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 546
 547 #endif
 548
 549 #define BOOT_TARGET_DEVICES(func) \
 550         func(USB, usb, 0) \
 551         func(MMC, mmc, 0) \
 552         func(SCSI, scsi, 0) \
 553         func(DHCP, dhcp, na)
 554 #include <config_distro_bootcmd.h>
 555
 556 #include <asm/fsl_secure_boot.h>
 557
 558 #endif /* __LS1088A_QDS_H */