include/configs/ls1046ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __LS1046ARDB_H__
   8 #define __LS1046ARDB_H__
   9
  10 #include "ls1046a_common.h"
  11
  12 /* Physical Memory Map */
  13
  14 #define SPD_EEPROM_ADDRESS              0x51
  15
  16 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  17
  18 #if defined(CONFIG_QSPI_BOOT)
  19 #define CONFIG_SYS_UBOOT_BASE           0x40100000
  20 #endif
  21
  22 #define CFG_SYS_NAND_BASE               0x7e800000
  23 #define CFG_SYS_NAND_BASE_PHYS  CFG_SYS_NAND_BASE
  24
  25 #define CFG_SYS_NAND_CSPR_EXT   (0x0)
  26 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
  27                                 | CSPR_PORT_SIZE_8      \
  28                                 | CSPR_MSEL_NAND        \
  29                                 | CSPR_V)
  30 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64 * 1024)
  31 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  32                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  33                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
  34                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  35                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
  36                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
  37                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  38
  39 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x7) | \
  40                                         FTIM0_NAND_TWP(0x18)   | \
  41                                         FTIM0_NAND_TWCHT(0x7) | \
  42                                         FTIM0_NAND_TWH(0xa))
  43 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
  44                                         FTIM1_NAND_TWBE(0x39)  | \
  45                                         FTIM1_NAND_TRR(0xe)   | \
  46                                         FTIM1_NAND_TRP(0x18))
  47 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0xf) | \
  48                                         FTIM2_NAND_TREH(0xa) | \
  49                                         FTIM2_NAND_TWHRE(0x1e))
  50 #define CFG_SYS_NAND_FTIM3              0x0
  51
  52 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
  53 #define CONFIG_MTD_NAND_VERIFY_WRITE
  54
  55 /*
  56  * CPLD
  57  */
  58 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
  59 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
  60
  61 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
  62 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
  63                                         CSPR_PORT_SIZE_8 | \
  64                                         CSPR_MSEL_GPCM | \
  65                                         CSPR_V)
  66 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
  67 #define CONFIG_SYS_CPLD_CSOR            CSOR_NOR_ADM_SHIFT(16)
  68
  69 /* CPLD Timing parameters for IFC GPCM */
  70 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0x0e) | \
  71                                         FTIM0_GPCM_TEADC(0x0e) | \
  72                                         FTIM0_GPCM_TEAHC(0x0e))
  73 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
  74                                         FTIM1_GPCM_TRAD(0x3f))
  75 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
  76                                         FTIM2_GPCM_TCH(0xf) | \
  77                                         FTIM2_GPCM_TWP(0x3E))
  78 #define CONFIG_SYS_CPLD_FTIM3           0x0
  79
  80 /* IFC Timing Params */
  81 #define CONFIG_SYS_CSPR0_EXT            CFG_SYS_NAND_CSPR_EXT
  82 #define CONFIG_SYS_CSPR0                CFG_SYS_NAND_CSPR
  83 #define CONFIG_SYS_AMASK0               CFG_SYS_NAND_AMASK
  84 #define CONFIG_SYS_CSOR0                CFG_SYS_NAND_CSOR
  85 #define CONFIG_SYS_CS0_FTIM0            CFG_SYS_NAND_FTIM0
  86 #define CONFIG_SYS_CS0_FTIM1            CFG_SYS_NAND_FTIM1
  87 #define CONFIG_SYS_CS0_FTIM2            CFG_SYS_NAND_FTIM2
  88 #define CONFIG_SYS_CS0_FTIM3            CFG_SYS_NAND_FTIM3
  89
  90 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
  91 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
  92 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
  93 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
  94 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
  95 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
  96 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
  97 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
  98
  99 /* EEPROM */
 100 #define I2C_RETIMER_ADDR                        0x18
 101
 102 /* PMIC */
 103
 104 /*
 105  * Environment
 106  */
 107 #define CFG_SYS_FSL_QSPI_BASE        0x40000000
 108
 109 #define AQR105_IRQ_MASK                 0x80000000
 110 /* FMan */
 111 #ifndef SPL_NO_FMAN
 112 #ifdef CONFIG_SYS_DPAA_FMAN
 113 #define RGMII_PHY1_ADDR                 0x1
 114 #define RGMII_PHY2_ADDR                 0x2
 115
 116 #define SGMII_PHY1_ADDR                 0x3
 117 #define SGMII_PHY2_ADDR                 0x4
 118
 119 #define FM1_10GEC1_PHY_ADDR             0x0
 120
 121 #define FDT_SEQ_MACADDR_FROM_ENV
 122 #endif
 123
 124 #endif
 125
 126 #ifndef SPL_NO_MISC
 127 #ifdef CONFIG_TFABOOT
 128 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 129                            "env exists secureboot && esbc_halt;;"
 130 #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "    \
 131                            "env exists secureboot && esbc_halt;"
 132 #endif
 133 #endif
 134
 135 #include <asm/fsl_secure_boot.h>
 136
 137 #endif /* __LS1046ARDB_H__ */