include/configs/ls1046aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1046AQDS_H__
   7 #define __LS1046AQDS_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 /* Physical Memory Map */
  12
  13 #define SPD_EEPROM_ADDRESS              0x51
  14
  15 #ifdef CONFIG_DDR_ECC
  16 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  17 #endif
  18
  19 #ifdef CONFIG_SYS_DPAA_FMAN
  20 #define RGMII_PHY1_ADDR         0x1
  21 #define RGMII_PHY2_ADDR         0x2
  22 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  23 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  24 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  25 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  26 /* PHY address on QSGMII riser card on slot 2 */
  27 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  28 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  29 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  30 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  31 #endif
  32
  33 /* IFC */
  34 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  35 /*
  36  * CFG_SYS_FLASH_BASE has the final address (core view)
  37  * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  38  * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  39  * CONFIG_TEXT_BASE is linked to 0x60000000 for booting
  40  */
  41 #define CFG_SYS_FLASH_BASE                      0x60000000
  42 #define CFG_SYS_FLASH_BASE_PHYS         CFG_SYS_FLASH_BASE
  43 #define CFG_SYS_FLASH_BASE_PHYS_EARLY   0x00000000
  44
  45 #ifdef CONFIG_MTD_NOR_FLASH
  46 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
  47 #endif
  48 #endif
  49
  50 /* LPUART */
  51 #ifdef CONFIG_LPUART
  52 #define CFG_UART_MUX_MASK       0x6
  53 #define CFG_UART_MUX_SHIFT      1
  54 #define CFG_LPUART_EN           0x2
  55 #endif
  56
  57 /*
  58  * IFC Definitions
  59  */
  60 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  61 #define CFG_SYS_NOR0_CSPR_EXT   (0x0)
  62 #define CFG_SYS_NOR0_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
  63                                 CSPR_PORT_SIZE_16 | \
  64                                 CSPR_MSEL_NOR | \
  65                                 CSPR_V)
  66 #define CFG_SYS_NOR1_CSPR_EXT   (0x0)
  67 #define CFG_SYS_NOR1_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
  68                                 + 0x8000000) | \
  69                                 CSPR_PORT_SIZE_16 | \
  70                                 CSPR_MSEL_NOR | \
  71                                 CSPR_V)
  72 #define CFG_SYS_NOR_AMASK               IFC_AMASK(128 * 1024 * 1024)
  73
  74 #define CFG_SYS_NOR_CSOR                (CSOR_NOR_ADM_SHIFT(4) | \
  75                                         CSOR_NOR_TRHZ_80)
  76 #define CFG_SYS_NOR_FTIM0               (FTIM0_NOR_TACSE(0x4) | \
  77                                         FTIM0_NOR_TEADC(0x5) | \
  78                                         FTIM0_NOR_TAVDS(0x6) | \
  79                                         FTIM0_NOR_TEAHC(0x5))
  80 #define CFG_SYS_NOR_FTIM1               (FTIM1_NOR_TACO(0x35) | \
  81                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  82                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  83 #define CFG_SYS_NOR_FTIM2               (FTIM2_NOR_TCS(0x8) | \
  84                                         FTIM2_NOR_TCH(0x8) | \
  85                                         FTIM2_NOR_TWPH(0xe) | \
  86                                         FTIM2_NOR_TWP(0x1c))
  87 #define CFG_SYS_NOR_FTIM3               0
  88
  89 #define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS, \
  90                                         CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
  91
  92 #define CFG_SYS_WRITE_SWAPPED_DATA
  93
  94 /*
  95  * NAND Flash Definitions
  96  */
  97
  98 #define CFG_SYS_NAND_BASE               0x7e800000
  99 #define CFG_SYS_NAND_BASE_PHYS  CFG_SYS_NAND_BASE
 100
 101 #define CFG_SYS_NAND_CSPR_EXT   (0x0)
 102
 103 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 104                                 | CSPR_PORT_SIZE_8      \
 105                                 | CSPR_MSEL_NAND        \
 106                                 | CSPR_V)
 107 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
 108 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 109                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 110                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
 111                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 112                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 113                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 114                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 115
 116 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x7) | \
 117                                         FTIM0_NAND_TWP(0x18)   | \
 118                                         FTIM0_NAND_TWCHT(0x7) | \
 119                                         FTIM0_NAND_TWH(0xa))
 120 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
 121                                         FTIM1_NAND_TWBE(0x39)  | \
 122                                         FTIM1_NAND_TRR(0xe)   | \
 123                                         FTIM1_NAND_TRP(0x18))
 124 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0xf) | \
 125                                         FTIM2_NAND_TREH(0xa) | \
 126                                         FTIM2_NAND_TWHRE(0x1e))
 127 #define CFG_SYS_NAND_FTIM3           0x0
 128
 129 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 130 #define CONFIG_MTD_NAND_VERIFY_WRITE
 131 #endif
 132
 133 #ifdef CONFIG_NAND_BOOT
 134 #define CFG_SYS_NAND_U_BOOT_SIZE        (768 << 10)
 135 #endif
 136
 137 #if defined(CONFIG_TFABOOT) || \
 138         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 139 #endif
 140
 141 /*
 142  * QIXIS Definitions
 143  */
 144
 145 #ifdef CONFIG_FSL_QIXIS
 146 #define QIXIS_BASE                      0x7fb00000
 147 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 148 #define CFG_SYS_I2C_FPGA_ADDR   0x66
 149 #define QIXIS_LBMAP_SWITCH              6
 150 #define QIXIS_LBMAP_MASK                0x0f
 151 #define QIXIS_LBMAP_SHIFT               0
 152 #define QIXIS_LBMAP_DFLTBANK            0x00
 153 #define QIXIS_LBMAP_ALTBANK             0x04
 154 #define QIXIS_LBMAP_NAND                0x09
 155 #define QIXIS_LBMAP_SD                  0x00
 156 #define QIXIS_LBMAP_SD_QSPI             0xff
 157 #define QIXIS_LBMAP_QSPI                0xff
 158 #define QIXIS_RCW_SRC_NAND              0x110
 159 #define QIXIS_RCW_SRC_SD                0x040
 160 #define QIXIS_RCW_SRC_QSPI              0x045
 161 #define QIXIS_RST_CTL_RESET             0x41
 162 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 163 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 164 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 165
 166 #define CFG_SYS_FPGA_CSPR_EXT   (0x0)
 167 #define CFG_SYS_FPGA_CSPR               (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 168                                         CSPR_PORT_SIZE_8 | \
 169                                         CSPR_MSEL_GPCM | \
 170                                         CSPR_V)
 171 #define CFG_SYS_FPGA_AMASK              IFC_AMASK(64 * 1024)
 172 #define CFG_SYS_FPGA_CSOR               (CSOR_NOR_ADM_SHIFT(4) | \
 173                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 174                                         CSOR_NOR_TRHZ_80)
 175
 176 /*
 177  * QIXIS Timing parameters for IFC GPCM
 178  */
 179 #define CFG_SYS_FPGA_FTIM0              (FTIM0_GPCM_TACSE(0xc) | \
 180                                         FTIM0_GPCM_TEADC(0x20) | \
 181                                         FTIM0_GPCM_TEAHC(0x10))
 182 #define CFG_SYS_FPGA_FTIM1              (FTIM1_GPCM_TACO(0x50) | \
 183                                         FTIM1_GPCM_TRAD(0x1f))
 184 #define CFG_SYS_FPGA_FTIM2              (FTIM2_GPCM_TCS(0x8) | \
 185                                         FTIM2_GPCM_TCH(0x8) | \
 186                                         FTIM2_GPCM_TWP(0xf0))
 187 #define CFG_SYS_FPGA_FTIM3              0x0
 188 #endif
 189
 190 #ifdef CONFIG_TFABOOT
 191 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 192 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR
 193 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 194 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 195 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 196 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 197 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 198 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 199 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR1_CSPR_EXT
 200 #define CFG_SYS_CSPR1           CFG_SYS_NOR1_CSPR
 201 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 202 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 203 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 204 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 205 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 206 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 207 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NAND_CSPR_EXT
 208 #define CFG_SYS_CSPR2           CFG_SYS_NAND_CSPR
 209 #define CFG_SYS_AMASK2          CFG_SYS_NAND_AMASK
 210 #define CFG_SYS_CSOR2           CFG_SYS_NAND_CSOR
 211 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NAND_FTIM0
 212 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NAND_FTIM1
 213 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NAND_FTIM2
 214 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NAND_FTIM3
 215 #define CFG_SYS_CSPR3_EXT               CFG_SYS_FPGA_CSPR_EXT
 216 #define CFG_SYS_CSPR3           CFG_SYS_FPGA_CSPR
 217 #define CFG_SYS_AMASK3          CFG_SYS_FPGA_AMASK
 218 #define CFG_SYS_CSOR3           CFG_SYS_FPGA_CSOR
 219 #define CFG_SYS_CS3_FTIM0               CFG_SYS_FPGA_FTIM0
 220 #define CFG_SYS_CS3_FTIM1               CFG_SYS_FPGA_FTIM1
 221 #define CFG_SYS_CS3_FTIM2               CFG_SYS_FPGA_FTIM2
 222 #define CFG_SYS_CS3_FTIM3               CFG_SYS_FPGA_FTIM3
 223 #else
 224 #ifdef CONFIG_NAND_BOOT
 225 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 226 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 227 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 228 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 229 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 230 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 231 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 232 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 233 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR0_CSPR_EXT
 234 #define CFG_SYS_CSPR1           CFG_SYS_NOR0_CSPR
 235 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 236 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 237 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 238 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 239 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 240 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 241 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NOR1_CSPR_EXT
 242 #define CFG_SYS_CSPR2           CFG_SYS_NOR1_CSPR
 243 #define CFG_SYS_AMASK2          CFG_SYS_NOR_AMASK
 244 #define CFG_SYS_CSOR2           CFG_SYS_NOR_CSOR
 245 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NOR_FTIM0
 246 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NOR_FTIM1
 247 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NOR_FTIM2
 248 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NOR_FTIM3
 249 #define CFG_SYS_CSPR3_EXT               CFG_SYS_FPGA_CSPR_EXT
 250 #define CFG_SYS_CSPR3           CFG_SYS_FPGA_CSPR
 251 #define CFG_SYS_AMASK3          CFG_SYS_FPGA_AMASK
 252 #define CFG_SYS_CSOR3           CFG_SYS_FPGA_CSOR
 253 #define CFG_SYS_CS3_FTIM0               CFG_SYS_FPGA_FTIM0
 254 #define CFG_SYS_CS3_FTIM1               CFG_SYS_FPGA_FTIM1
 255 #define CFG_SYS_CS3_FTIM2               CFG_SYS_FPGA_FTIM2
 256 #define CFG_SYS_CS3_FTIM3               CFG_SYS_FPGA_FTIM3
 257 #else
 258 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 259 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR
 260 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 261 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 262 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 263 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 264 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 265 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 266 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR1_CSPR_EXT
 267 #define CFG_SYS_CSPR1           CFG_SYS_NOR1_CSPR
 268 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 269 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 270 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 271 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 272 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 273 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 274 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NAND_CSPR_EXT
 275 #define CFG_SYS_CSPR2           CFG_SYS_NAND_CSPR
 276 #define CFG_SYS_AMASK2          CFG_SYS_NAND_AMASK
 277 #define CFG_SYS_CSOR2           CFG_SYS_NAND_CSOR
 278 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NAND_FTIM0
 279 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NAND_FTIM1
 280 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NAND_FTIM2
 281 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NAND_FTIM3
 282 #define CFG_SYS_CSPR3_EXT               CFG_SYS_FPGA_CSPR_EXT
 283 #define CFG_SYS_CSPR3           CFG_SYS_FPGA_CSPR
 284 #define CFG_SYS_AMASK3          CFG_SYS_FPGA_AMASK
 285 #define CFG_SYS_CSOR3           CFG_SYS_FPGA_CSOR
 286 #define CFG_SYS_CS3_FTIM0               CFG_SYS_FPGA_FTIM0
 287 #define CFG_SYS_CS3_FTIM1               CFG_SYS_FPGA_FTIM1
 288 #define CFG_SYS_CS3_FTIM2               CFG_SYS_FPGA_FTIM2
 289 #define CFG_SYS_CS3_FTIM3               CFG_SYS_FPGA_FTIM3
 290 #endif
 291 #endif
 292
 293 /*
 294  * I2C bus multiplexer
 295  */
 296 #define I2C_MUX_PCA_ADDR_PRI            0x77
 297 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 298 #define I2C_RETIMER_ADDR                0x18
 299 #define I2C_MUX_CH_DEFAULT              0x8
 300 #define I2C_MUX_CH_CH7301               0xC
 301 #define I2C_MUX_CH5                     0xD
 302 #define I2C_MUX_CH6                     0xE
 303 #define I2C_MUX_CH7                     0xF
 304
 305 #define I2C_MUX_CH_VOL_MONITOR 0xa
 306
 307 /* Voltage monitor on channel 2*/
 308 #define I2C_VOL_MONITOR_ADDR           0x40
 309 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 310 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 311 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 312
 313 /* The lowest and highest voltage allowed for LS1046AQDS */
 314 #define VDD_MV_MIN                      819
 315 #define VDD_MV_MAX                      1212
 316
 317 /*
 318  * Miscellaneous configurable options
 319  */
 320
 321 /*
 322  * Environment
 323  */
 324
 325 #ifdef CONFIG_TFABOOT
 326 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "   \
 327                            "env exists secureboot && esbc_halt;;"
 328 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd"      \
 329                            "env exists secureboot && esbc_halt;;"
 330 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 331                            "env exists secureboot && esbc_halt;;"
 332 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 333                            "env exists secureboot && esbc_halt;;"
 334 #endif
 335
 336 #include <asm/fsl_secure_boot.h>
 337
 338 #endif /* __LS1046AQDS_H__ */