include/configs/ls1046aqds.h

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1046AQDS_H__
   8 #define __LS1046AQDS_H__
   9
  10 #include "ls1046a_common.h"
  11
  12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
  13 #define CONFIG_SYS_TEXT_BASE            0x82000000
  14 #elif defined(CONFIG_QSPI_BOOT)
  15 #define CONFIG_SYS_TEXT_BASE            0x40010000
  16 #else
  17 #define CONFIG_SYS_TEXT_BASE            0x60100000
  18 #endif
  19
  20 #ifndef __ASSEMBLY__
  21 unsigned long get_board_sys_clk(void);
  22 unsigned long get_board_ddr_clk(void);
  23 #endif
  24
  25 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  26 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  27
  28 #define CONFIG_SKIP_LOWLEVEL_INIT
  29
  30 #define CONFIG_LAYERSCAPE_NS_ACCESS
  31
  32 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  33 /* Physical Memory Map */
  34 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  35 #define CONFIG_NR_DRAM_BANKS            2
  36
  37 #define CONFIG_DDR_SPD
  38 #define SPD_EEPROM_ADDRESS              0x51
  39 #define CONFIG_SYS_SPD_BUS_NUM          0
  40
  41 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  42
  43 #define CONFIG_DDR_ECC
  44 #ifdef CONFIG_DDR_ECC
  45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  46 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  47 #endif
  48
  49 /* DSPI */
  50 #ifdef CONFIG_FSL_DSPI
  51 #define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
  52 #define CONFIG_SPI_FLASH_SST            /* cs1 */
  53 #define CONFIG_SPI_FLASH_EON            /* cs2 */
  54 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  55 #define CONFIG_SF_DEFAULT_BUS           1
  56 #define CONFIG_SF_DEFAULT_CS            0
  57 #endif
  58 #endif
  59
  60 /* QSPI */
  61 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  62 #ifdef CONFIG_FSL_QSPI
  63 #define CONFIG_SPI_FLASH_SPANSION
  64 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
  65 #define FSL_QSPI_FLASH_NUM              2
  66 #endif
  67 #endif
  68
  69 #ifdef CONFIG_SYS_DPAA_FMAN
  70 #define CONFIG_FMAN_ENET
  71 #define CONFIG_PHYLIB
  72 #define CONFIG_PHY_VITESSE
  73 #define CONFIG_PHY_REALTEK
  74 #define CONFIG_PHYLIB_10G
  75 #define RGMII_PHY1_ADDR         0x1
  76 #define RGMII_PHY2_ADDR         0x2
  77 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  78 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  79 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  80 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  81 /* PHY address on QSGMII riser card on slot 2 */
  82 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  83 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  84 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  85 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  86 #endif
  87
  88 #ifdef CONFIG_RAMBOOT_PBL
  89 #define CONFIG_SYS_FSL_PBL_PBI \
  90         board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
  91 #endif
  92
  93 #ifdef CONFIG_NAND_BOOT
  94 #define CONFIG_SYS_FSL_PBL_RCW \
  95         board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
  96 #endif
  97
  98 #ifdef CONFIG_SD_BOOT
  99 #ifdef CONFIG_SD_BOOT_QSPI
 100 #define CONFIG_SYS_FSL_PBL_RCW \
 101         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
 102 #else
 103 #define CONFIG_SYS_FSL_PBL_RCW \
 104         board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
 105 #endif
 106 #endif
 107
 108 /* IFC */
 109 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 110 #define CONFIG_FSL_IFC
 111 /*
 112  * CONFIG_SYS_FLASH_BASE has the final address (core view)
 113  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 114  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 115  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 116  */
 117 #define CONFIG_SYS_FLASH_BASE                   0x60000000
 118 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
 119 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 120
 121 #ifndef CONFIG_SYS_NO_FLASH
 122 #define CONFIG_FLASH_CFI_DRIVER
 123 #define CONFIG_SYS_FLASH_CFI
 124 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 125 #define CONFIG_SYS_FLASH_QUIET_TEST
 126 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 127 #endif
 128 #endif
 129
 130 /* LPUART */
 131 #ifdef CONFIG_LPUART
 132 #define CONFIG_LPUART_32B_REG
 133 #define CFG_UART_MUX_MASK       0x6
 134 #define CFG_UART_MUX_SHIFT      1
 135 #define CFG_LPUART_EN           0x2
 136 #endif
 137
 138 /* USB */
 139 #define CONFIG_HAS_FSL_XHCI_USB
 140 #ifdef CONFIG_HAS_FSL_XHCI_USB
 141 #define CONFIG_USB_XHCI_HCD
 142 #define CONFIG_USB_XHCI_FSL
 143 #define CONFIG_USB_XHCI_DWC3
 144 #define CONFIG_USB_MAX_CONTROLLER_COUNT         3
 145 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 146 #define CONFIG_CMD_USB
 147 #define CONFIG_USB_STORAGE
 148 #endif
 149
 150 /* SATA */
 151 #define CONFIG_LIBATA
 152 #define CONFIG_SCSI_AHCI
 153 #define CONFIG_SCSI_AHCI_PLAT
 154 #define CONFIG_SCSI
 155 #define CONFIG_DOS_PARTITION
 156
 157 #define CONFIG_PARTITION_UUIDS
 158 #define CONFIG_EFI_PARTITION
 159 #define CONFIG_CMD_GPT
 160
 161 /* EEPROM */
 162 #define CONFIG_ID_EEPROM
 163 #define CONFIG_SYS_I2C_EEPROM_NXID
 164 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 165 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 167 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 168 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 169
 170 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
 171
 172 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
 173 #define CONFIG_SYS_SCSI_MAX_LUN                 1
 174 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 175                                                 CONFIG_SYS_SCSI_MAX_LUN)
 176
 177 /*
 178  * IFC Definitions
 179  */
 180 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 181 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 182 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 183                                 CSPR_PORT_SIZE_16 | \
 184                                 CSPR_MSEL_NOR | \
 185                                 CSPR_V)
 186 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 187 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 188                                 + 0x8000000) | \
 189                                 CSPR_PORT_SIZE_16 | \
 190                                 CSPR_MSEL_NOR | \
 191                                 CSPR_V)
 192 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 193
 194 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 195                                         CSOR_NOR_TRHZ_80)
 196 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 197                                         FTIM0_NOR_TEADC(0x5) | \
 198                                         FTIM0_NOR_TEAHC(0x5))
 199 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 200                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 201                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 202 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 203                                         FTIM2_NOR_TCH(0x4) | \
 204                                         FTIM2_NOR_TWPH(0xe) | \
 205                                         FTIM2_NOR_TWP(0x1c))
 206 #define CONFIG_SYS_NOR_FTIM3            0
 207
 208 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 209 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 210 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 211 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 212
 213 #define CONFIG_SYS_FLASH_EMPTY_INFO
 214 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 215                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 216
 217 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 218 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 219
 220 /*
 221  * NAND Flash Definitions
 222  */
 223 #define CONFIG_NAND_FSL_IFC
 224
 225 #define CONFIG_SYS_NAND_BASE            0x7e800000
 226 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 227
 228 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 229
 230 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 231                                 | CSPR_PORT_SIZE_8      \
 232                                 | CSPR_MSEL_NAND        \
 233                                 | CSPR_V)
 234 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 235 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 236                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 237                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
 238                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 239                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 240                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 241                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 242
 243 #define CONFIG_SYS_NAND_ONFI_DETECTION
 244
 245 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 246                                         FTIM0_NAND_TWP(0x18)   | \
 247                                         FTIM0_NAND_TWCHT(0x7) | \
 248                                         FTIM0_NAND_TWH(0xa))
 249 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 250                                         FTIM1_NAND_TWBE(0x39)  | \
 251                                         FTIM1_NAND_TRR(0xe)   | \
 252                                         FTIM1_NAND_TRP(0x18))
 253 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 254                                         FTIM2_NAND_TREH(0xa) | \
 255                                         FTIM2_NAND_TWHRE(0x1e))
 256 #define CONFIG_SYS_NAND_FTIM3           0x0
 257
 258 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 259 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 260 #define CONFIG_MTD_NAND_VERIFY_WRITE
 261 #define CONFIG_CMD_NAND
 262
 263 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
 264 #endif
 265
 266 #ifdef CONFIG_NAND_BOOT
 267 #define CONFIG_SPL_PAD_TO               0x40000         /* block aligned */
 268 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 269 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
 270 #endif
 271
 272 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 273 #define CONFIG_QIXIS_I2C_ACCESS
 274 #define CONFIG_SYS_I2C_EARLY_INIT
 275 #define CONFIG_SYS_NO_FLASH
 276 #endif
 277
 278 /*
 279  * QIXIS Definitions
 280  */
 281 #define CONFIG_FSL_QIXIS
 282
 283 #ifdef CONFIG_FSL_QIXIS
 284 #define QIXIS_BASE                      0x7fb00000
 285 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 286 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 287 #define QIXIS_LBMAP_SWITCH              6
 288 #define QIXIS_LBMAP_MASK                0x0f
 289 #define QIXIS_LBMAP_SHIFT               0
 290 #define QIXIS_LBMAP_DFLTBANK            0x00
 291 #define QIXIS_LBMAP_ALTBANK             0x04
 292 #define QIXIS_LBMAP_NAND                0x09
 293 #define QIXIS_LBMAP_SD                  0x00
 294 #define QIXIS_LBMAP_SD_QSPI             0xff
 295 #define QIXIS_LBMAP_QSPI                0xff
 296 #define QIXIS_RCW_SRC_NAND              0x110
 297 #define QIXIS_RCW_SRC_SD                0x040
 298 #define QIXIS_RCW_SRC_QSPI              0x045
 299 #define QIXIS_RST_CTL_RESET             0x41
 300 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 301 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 302 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 303
 304 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 305 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 306                                         CSPR_PORT_SIZE_8 | \
 307                                         CSPR_MSEL_GPCM | \
 308                                         CSPR_V)
 309 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 310 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 311                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 312                                         CSOR_NOR_TRHZ_80)
 313
 314 /*
 315  * QIXIS Timing parameters for IFC GPCM
 316  */
 317 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 318                                         FTIM0_GPCM_TEADC(0x20) | \
 319                                         FTIM0_GPCM_TEAHC(0x10))
 320 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 321                                         FTIM1_GPCM_TRAD(0x1f))
 322 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 323                                         FTIM2_GPCM_TCH(0x8) | \
 324                                         FTIM2_GPCM_TWP(0xf0))
 325 #define CONFIG_SYS_FPGA_FTIM3           0x0
 326 #endif
 327
 328 #ifdef CONFIG_NAND_BOOT
 329 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 330 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 331 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 332 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 333 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 334 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 335 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 336 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 337 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 338 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 339 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 340 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 341 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 342 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 343 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 344 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 345 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 346 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 347 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 348 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 349 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 350 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 351 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 352 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 353 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 354 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 355 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 356 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 357 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 358 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 359 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 360 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 361 #else
 362 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 363 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 364 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 365 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 366 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 367 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 368 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 369 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 370 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 371 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 372 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 373 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 374 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 375 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 376 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 377 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 378 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 379 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 380 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 381 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 382 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 383 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 384 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 385 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 386 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 387 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 388 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 389 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 390 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 391 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 392 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 393 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 394 #endif
 395
 396 /*
 397  * I2C bus multiplexer
 398  */
 399 #define I2C_MUX_PCA_ADDR_PRI            0x77
 400 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 401 #define I2C_RETIMER_ADDR                0x18
 402 #define I2C_MUX_CH_DEFAULT              0x8
 403 #define I2C_MUX_CH_CH7301               0xC
 404 #define I2C_MUX_CH5                     0xD
 405 #define I2C_MUX_CH6                     0xE
 406 #define I2C_MUX_CH7                     0xF
 407
 408 #define I2C_MUX_CH_VOL_MONITOR 0xa
 409
 410 /* Voltage monitor on channel 2*/
 411 #define I2C_VOL_MONITOR_ADDR           0x40
 412 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 413 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 414 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 415
 416 #define CONFIG_VID_FLS_ENV              "ls1046aqds_vdd_mv"
 417 #ifndef CONFIG_SPL_BUILD
 418 #define CONFIG_VID
 419 #endif
 420 #define CONFIG_VOL_MONITOR_IR36021_SET
 421 #define CONFIG_VOL_MONITOR_INA220
 422 /* The lowest and highest voltage allowed for LS1046AQDS */
 423 #define VDD_MV_MIN                      819
 424 #define VDD_MV_MAX                      1212
 425
 426 /*
 427  * Miscellaneous configurable options
 428  */
 429 #define CONFIG_MISC_INIT_R
 430 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 431 #define CONFIG_AUTO_COMPLETE
 432 #define CONFIG_SYS_PBSIZE               \
 433                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 434 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 435
 436 #define CONFIG_SYS_MEMTEST_START        0x80000000
 437 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 438
 439 #define CONFIG_SYS_HZ                   1000
 440
 441 /*
 442  * Stack sizes
 443  * The stack sizes are set up in start.S using the settings below
 444  */
 445 #define CONFIG_STACKSIZE                (30 * 1024)
 446
 447 #define CONFIG_SYS_INIT_SP_OFFSET \
 448         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 449
 450 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 451
 452 /*
 453  * Environment
 454  */
 455 #define CONFIG_ENV_OVERWRITE
 456
 457 #ifdef CONFIG_NAND_BOOT
 458 #define CONFIG_ENV_IS_IN_NAND
 459 #define CONFIG_ENV_SIZE                 0x2000
 460 #define CONFIG_ENV_OFFSET               (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 461 #elif defined(CONFIG_SD_BOOT)
 462 #define CONFIG_ENV_OFFSET               (1024 * 1024)
 463 #define CONFIG_ENV_IS_IN_MMC
 464 #define CONFIG_SYS_MMC_ENV_DEV          0
 465 #define CONFIG_ENV_SIZE                 0x2000
 466 #elif defined(CONFIG_QSPI_BOOT)
 467 #define CONFIG_ENV_IS_IN_SPI_FLASH
 468 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 469 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 470 #define CONFIG_ENV_SECT_SIZE            0x10000
 471 #else
 472 #define CONFIG_ENV_IS_IN_FLASH
 473 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
 474 #define CONFIG_ENV_SECT_SIZE            0x20000
 475 #define CONFIG_ENV_SIZE                 0x20000
 476 #endif
 477
 478 #define CONFIG_CMDLINE_TAG
 479
 480 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 481 #define CONFIG_BOOTCOMMAND              "sf probe && sf read $kernel_load "    \
 482                                         "e0000 f00000 && bootm $kernel_load"
 483 #else
 484 #define CONFIG_BOOTCOMMAND              "cp.b $kernel_start $kernel_load "     \
 485                                         "$kernel_size && bootm $kernel_load"
 486 #endif
 487
 488 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 489 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \
 490                         "14m(free)"
 491 #else
 492 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
 493                         "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
 494                         "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
 495                         "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
 496                         "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
 497                         "40m(nor_bank4_fit);7e800000.flash:" \
 498                         "4m(nand_uboot),36m(nand_kernel)," \
 499                         "472m(nand_free);spi0.0:2m(uboot)," \
 500                         "14m(free)"
 501 #endif
 502
 503 #include <asm/fsl_secure_boot.h>
 504
 505 #endif /* __LS1046AQDS_H__ */