include/configs/ls1046afrwy.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2019-2020 NXP
   4  */
   5
   6 #ifndef __LS1046AFRWY_H__
   7 #define __LS1046AFRWY_H__
   8
   9 #include "ls1046a_common.h"
  10
  11 #define CFG_SYS_UBOOT_BASE              0x40100000
  12
  13 /*
  14  * NAND Flash Definitions
  15  */
  16
  17 #define CFG_SYS_NAND_BASE               0x7e800000
  18 #define CFG_SYS_NAND_BASE_PHYS  CFG_SYS_NAND_BASE
  19
  20 #define CFG_SYS_NAND_CSPR_EXT   (0x0)
  21 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
  22                                 | CSPR_PORT_SIZE_8      \
  23                                 | CSPR_MSEL_NAND        \
  24                                 | CSPR_V)
  25 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64 * 1024)
  26 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  27                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  28                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  29                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  30                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  31                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
  32                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  33
  34 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x7) | \
  35                                         FTIM0_NAND_TWP(0x18)   | \
  36                                         FTIM0_NAND_TWCHT(0x7) | \
  37                                         FTIM0_NAND_TWH(0xa))
  38 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
  39                                         FTIM1_NAND_TWBE(0x39)  | \
  40                                         FTIM1_NAND_TRR(0xe)   | \
  41                                         FTIM1_NAND_TRP(0x18))
  42 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0xf) | \
  43                                         FTIM2_NAND_TREH(0xa) | \
  44                                         FTIM2_NAND_TWHRE(0x1e))
  45 #define CFG_SYS_NAND_FTIM3              0x0
  46
  47 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
  48
  49 /* IFC Timing Params */
  50 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
  51 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
  52 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
  53 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
  54 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
  55 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
  56 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
  57 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
  58
  59 /* EEPROM */
  60 #define I2C_RETIMER_ADDR                        0x18
  61
  62 /* I2C bus multiplexer */
  63 #define I2C_MUX_PCA_ADDR_PRI                    0x77 /* Primary Mux*/
  64 #define I2C_MUX_CH_DEFAULT                      0x1 /* Channel 0*/
  65 #define I2C_MUX_CH_RTC                          0x1 /* Channel 0*/
  66
  67 /* RTC */
  68 #define CFG_SYS_I2C_RTC_ADDR            0x51  /* Channel 0 I2C bus 0*/
  69 #define CFG_SYS_RTC_BUS_NUM                     0
  70
  71 /*
  72  * Environment
  73  */
  74 #define CFG_SYS_FSL_QSPI_BASE   0x40000000
  75
  76 #undef BOOT_TARGET_DEVICES
  77 #define BOOT_TARGET_DEVICES(func) \
  78         func(MMC, mmc, 0) \
  79         func(USB, usb, 0) \
  80         func(DHCP, dhcp, na)
  81
  82 /* FMan */
  83 #ifdef CONFIG_SYS_DPAA_FMAN
  84
  85 #define QSGMII_PORT1_PHY_ADDR           0x1c
  86 #define QSGMII_PORT2_PHY_ADDR           0x1d
  87 #define QSGMII_PORT3_PHY_ADDR           0x1e
  88 #define QSGMII_PORT4_PHY_ADDR           0x1f
  89
  90 #define FDT_SEQ_MACADDR_FROM_ENV
  91
  92 #endif
  93
  94 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
  95                            "env exists secureboot && esbc_halt;;"
  96 #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "    \
  97                            "env exists secureboot && esbc_halt;"
  98
  99 #include <asm/fsl_secure_boot.h>
 100
 101 #endif /* __LS1046AFRWY_H__ */