include/configs/ls1046a_common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 Freescale Semiconductor
   4  * Copyright 2019-2021 NXP
   5  */
   6
   7 #ifndef __LS1046A_COMMON_H
   8 #define __LS1046A_COMMON_H
   9
  10 /* SPL build */
  11 #ifdef CONFIG_SPL_BUILD
  12 #define SPL_NO_QBMAN
  13 #define SPL_NO_FMAN
  14 #define SPL_NO_ENV
  15 #define SPL_NO_MISC
  16 #define SPL_NO_QSPI
  17 #define SPL_NO_USB
  18 #define SPL_NO_SATA
  19 #endif
  20 #if defined(CONFIG_SPL_BUILD) && \
  21         (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
  22 #define SPL_NO_MMC
  23 #endif
  24 #if defined(CONFIG_SPL_BUILD)           && \
  25         !defined(CONFIG_SPL_FSL_LS_PPA)
  26 #define SPL_NO_IFC
  27 #endif
  28
  29 #define CONFIG_REMAKE_ELF
  30 #define CONFIG_GICV2
  31
  32 #include <asm/arch/config.h>
  33 #include <asm/arch/stream_id_lsch2.h>
  34
  35 /* Link Definitions */
  36 #ifdef CONFIG_TFABOOT
  37 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SYS_TEXT_BASE
  38 #else
  39 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  40 #endif
  41
  42 #define CONFIG_SKIP_LOWLEVEL_INIT
  43
  44 #define CONFIG_VERY_BIG_RAM
  45 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
  46 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  47 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  48 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
  49
  50 #define CPU_RELEASE_ADDR               secondary_boot_addr
  51
  52 /* Generic Timer Definitions */
  53 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  54
  55 /* Size of malloc() pool */
  56 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 1024 * 1024)
  57
  58 /* Serial Port */
  59 #define CONFIG_SYS_NS16550_SERIAL
  60 #define CONFIG_SYS_NS16550_REG_SIZE     1
  61 #define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
  62
  63 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  64
  65 /* SD boot SPL */
  66 #ifdef CONFIG_SD_BOOT
  67 #define CONFIG_SPL_MAX_SIZE             0x1f000         /* 124 KiB */
  68 #define CONFIG_SPL_STACK                0x10020000
  69 #define CONFIG_SPL_PAD_TO               0x21000         /* 132 KiB */
  70 #define CONFIG_SPL_BSS_START_ADDR       0x8f000000
  71 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  72 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
  73                                         CONFIG_SPL_BSS_MAX_SIZE)
  74 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  75
  76 #ifdef CONFIG_NXP_ESBC
  77 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  78 /*
  79  * HDR would be appended at end of image and copied to DDR along
  80  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  81  * size increases then increase this size in case of secure boot as
  82  * it uses raw u-boot image instead of fit image.
  83  */
  84 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  85 #else
  86 #define CONFIG_SYS_MONITOR_LEN          0x100000
  87 #endif /* ifdef CONFIG_NXP_ESBC */
  88 #endif
  89
  90 #if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
  91 #define CONFIG_SPL_TARGET               "spl/u-boot-spl.pbl"
  92 #define CONFIG_SPL_MAX_SIZE             0x1f000
  93 #define CONFIG_SPL_STACK                0x10020000
  94 #define CONFIG_SPL_PAD_TO               0x20000
  95 #define CONFIG_SPL_BSS_START_ADDR       0x8f000000
  96 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  97 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
  98                                         CONFIG_SPL_BSS_MAX_SIZE)
  99 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 100 #define CONFIG_SYS_MONITOR_LEN          0x100000
 101 #endif
 102
 103 /* NAND SPL */
 104 #ifdef CONFIG_NAND_BOOT
 105 #define CONFIG_SPL_PBL_PAD
 106 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 107 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 108 #define CONFIG_SPL_ENV_SUPPORT
 109 #define CONFIG_SPL_WATCHDOG
 110 #define CONFIG_SPL_I2C
 111 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 112
 113 #define CONFIG_SPL_NAND_SUPPORT
 114 #define CONFIG_SPL_DRIVERS_MISC
 115 #define CONFIG_SPL_MAX_SIZE             0x17000         /* 90 KiB */
 116 #define CONFIG_SPL_STACK                0x1001f000
 117 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 118 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 119
 120 #define CONFIG_SPL_BSS_START_ADDR       0x8f000000
 121 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 122 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
 123                                         CONFIG_SPL_BSS_MAX_SIZE)
 124 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 125 #define CONFIG_SYS_MONITOR_LEN          0xa0000
 126 #endif
 127
 128 /* GPIO */
 129 #ifdef CONFIG_DM_GPIO
 130 #ifndef CONFIG_MPC8XXX_GPIO
 131 #define CONFIG_MPC8XXX_GPIO
 132 #endif
 133 #endif
 134
 135 /* I2C */
 136 #if !CONFIG_IS_ENABLED(DM_I2C)
 137 #define CONFIG_SYS_I2C_LEGACY
 138 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 139 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 140 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 141 #define CONFIG_SYS_I2C_MXC_I2C4         /* enable I2C bus 4 */
 142 #else
 143 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 144 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
 145 #endif
 146
 147 /* PCIe */
 148 #define CONFIG_PCIE1            /* PCIE controller 1 */
 149 #define CONFIG_PCIE2            /* PCIE controller 2 */
 150 #define CONFIG_PCIE3            /* PCIE controller 3 */
 151
 152 #ifdef CONFIG_PCI
 153 #define CONFIG_PCI_SCAN_SHOW
 154 #endif
 155
 156 /* SATA */
 157 #ifndef SPL_NO_SATA
 158 #define CONFIG_SCSI_AHCI_PLAT
 159
 160 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
 161
 162 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
 163 #define CONFIG_SYS_SCSI_MAX_LUN                 1
 164 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 165                                                 CONFIG_SYS_SCSI_MAX_LUN)
 166 #endif
 167
 168 /* FMan ucode */
 169 #ifndef SPL_NO_FMAN
 170 #define CONFIG_SYS_DPAA_FMAN
 171 #ifdef CONFIG_SYS_DPAA_FMAN
 172 #define CONFIG_SYS_FM_MURAM_SIZE        0x60000
 173 #endif
 174
 175 #ifdef CONFIG_TFABOOT
 176 #define CONFIG_SYS_FMAN_FW_ADDR         0x900000
 177 #else
 178 #ifdef CONFIG_SD_BOOT
 179 /*
 180  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 181  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 182  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
 183  */
 184 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x4800)
 185 #elif defined(CONFIG_QSPI_BOOT)
 186 #define CONFIG_SYS_FMAN_FW_ADDR         0x40900000
 187 #elif defined(CONFIG_NAND_BOOT)
 188 #define CONFIG_SYS_FMAN_FW_ADDR         (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
 189 #else
 190 #define CONFIG_SYS_FMAN_FW_ADDR         0x60900000
 191 #endif
 192 #endif
 193 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 194 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 195 #endif
 196
 197 /* Miscellaneous configurable options */
 198 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 199
 200 #define CONFIG_HWCONFIG
 201 #define HWCONFIG_BUFFER_SIZE            128
 202
 203 #ifndef CONFIG_SPL_BUILD
 204 #define BOOT_TARGET_DEVICES(func) \
 205         func(SCSI, scsi, 0) \
 206         func(MMC, mmc, 0) \
 207         func(USB, usb, 0) \
 208         func(DHCP, dhcp, na)
 209 #include <config_distro_bootcmd.h>
 210 #endif
 211
 212 #if defined(CONFIG_TARGET_LS1046AFRWY)
 213 #define LS1046A_BOOT_SRC_AND_HDR\
 214         "boot_scripts=ls1046afrwy_boot.scr\0"   \
 215         "boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
 216 #elif defined(CONFIG_TARGET_LS1046AQDS)
 217 #define LS1046A_BOOT_SRC_AND_HDR\
 218         "boot_scripts=ls1046aqds_boot.scr\0"    \
 219         "boot_script_hdr=hdr_ls1046aqds_bs.out\0"
 220 #else
 221 #define LS1046A_BOOT_SRC_AND_HDR\
 222         "boot_scripts=ls1046ardb_boot.scr\0"    \
 223         "boot_script_hdr=hdr_ls1046ardb_bs.out\0"
 224 #endif
 225 #ifndef SPL_NO_MISC
 226 /* Initial environment variables */
 227 #define CONFIG_EXTRA_ENV_SETTINGS               \
 228         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 229         "ramdisk_addr=0x800000\0"               \
 230         "ramdisk_size=0x2000000\0"              \
 231         "bootm_size=0x10000000\0"               \
 232         "fdt_addr=0x64f00000\0"                 \
 233         "kernel_addr=0x61000000\0"              \
 234         "scriptaddr=0x80000000\0"               \
 235         "scripthdraddr=0x80080000\0"            \
 236         "fdtheader_addr_r=0x80100000\0"         \
 237         "kernelheader_addr_r=0x80200000\0"      \
 238         "load_addr=0xa0000000\0"            \
 239         "kernel_addr_r=0x81000000\0"            \
 240         "fdt_addr_r=0x90000000\0"               \
 241         "ramdisk_addr_r=0xa0000000\0"           \
 242         "kernel_start=0x1000000\0"              \
 243         "kernelheader_start=0x600000\0"         \
 244         "kernel_load=0xa0000000\0"              \
 245         "kernel_size=0x2800000\0"               \
 246         "kernelheader_size=0x40000\0"           \
 247         "kernel_addr_sd=0x8000\0"               \
 248         "kernel_size_sd=0x14000\0"              \
 249         "kernelhdr_addr_sd=0x3000\0"            \
 250         "kernelhdr_size_sd=0x10\0"              \
 251         "console=ttyS0,115200\0"                \
 252          CONFIG_MTDPARTS_DEFAULT "\0"           \
 253         BOOTENV                                 \
 254         LS1046A_BOOT_SRC_AND_HDR                \
 255         "scan_dev_for_boot_part="               \
 256                 "part list ${devtype} ${devnum} devplist; "   \
 257                 "env exists devplist || setenv devplist 1; "  \
 258                 "for distro_bootpart in ${devplist}; do "     \
 259                   "if fstype ${devtype} "                  \
 260                         "${devnum}:${distro_bootpart} "      \
 261                         "bootfstype; then "                  \
 262                         "run scan_dev_for_boot; "            \
 263                   "fi; "                                   \
 264                 "done\0"                                   \
 265         "boot_a_script="                                  \
 266                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 267                         "${scriptaddr} ${prefix}${script}; "    \
 268                 "env exists secureboot && load ${devtype} "     \
 269                         "${devnum}:${distro_bootpart} "         \
 270                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 271                         "env exists secureboot "        \
 272                         "&& esbc_validate ${scripthdraddr};"    \
 273                 "source ${scriptaddr}\0"          \
 274         "qspi_bootcmd=echo Trying load from qspi..;"      \
 275                 "sf probe && sf read $load_addr "         \
 276                 "$kernel_start $kernel_size; env exists secureboot "    \
 277                 "&& sf read $kernelheader_addr_r $kernelheader_start "  \
 278                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 279                 "bootm $load_addr#$board\0"             \
 280         "nand_bootcmd=echo Trying load from nand..;"      \
 281                 "nand info; nand read $load_addr "         \
 282                 "$kernel_start $kernel_size; env exists secureboot "    \
 283                 "&& nand read $kernelheader_addr_r $kernelheader_start " \
 284                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 285                 "bootm $load_addr#$board\0"             \
 286         "nor_bootcmd=echo Trying load from nor..;"      \
 287                 "cp.b $kernel_addr $load_addr "         \
 288                 "$kernel_size; env exists secureboot "  \
 289                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
 290                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 291                 "bootm $load_addr#$board\0"     \
 292         "sd_bootcmd=echo Trying load from SD ..;"       \
 293                 "mmcinfo; mmc read $load_addr "         \
 294                 "$kernel_addr_sd $kernel_size_sd && "   \
 295                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
 296                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 297                 " && esbc_validate ${kernelheader_addr_r};"     \
 298                 "bootm $load_addr#$board\0"
 299
 300 #endif
 301
 302 /* Monitor Command Prompt */
 303 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 304
 305 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 306
 307 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 308
 309 #include <asm/arch/soc.h>
 310
 311 #endif /* __LS1046A_COMMON_H */