include/configs/ls1043ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015 Freescale Semiconductor
   4  */
   5
   6 #ifndef __LS1043ARDB_H__
   7 #define __LS1043ARDB_H__
   8
   9 #include "ls1043a_common.h"
  10
  11 #define CONFIG_SYS_CLK_FREQ             100000000
  12 #define CONFIG_DDR_CLK_FREQ             100000000
  13
  14 #define CONFIG_LAYERSCAPE_NS_ACCESS
  15
  16 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  17 /* Physical Memory Map */
  18 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  19
  20 #define CONFIG_SYS_SPD_BUS_NUM          0
  21
  22 #ifndef CONFIG_SPL
  23 #define CONFIG_SYS_DDR_RAW_TIMING
  24 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  25 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  26 #endif
  27
  28 #ifdef CONFIG_RAMBOOT_PBL
  29 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
  30 #endif
  31
  32 #ifdef CONFIG_NAND_BOOT
  33 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
  34 #endif
  35
  36 #ifdef CONFIG_SD_BOOT
  37 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
  38 #define CONFIG_SYS_SPL_ARGS_ADDR        0x90000000
  39 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000
  40 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR   0x500
  41 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS  30
  42 #endif
  43
  44 /*
  45  * NOR Flash Definitions
  46  */
  47 #define CONFIG_SYS_NOR_CSPR_EXT         (0x0)
  48 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  49 #define CONFIG_SYS_NOR_CSPR                                     \
  50         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  51         CSPR_PORT_SIZE_16                                       | \
  52         CSPR_MSEL_NOR                                           | \
  53         CSPR_V)
  54
  55 /* NOR Flash Timing Params */
  56 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  57                                         CSOR_NOR_TRHZ_80)
  58 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
  59                                         FTIM0_NOR_TEADC(0x1) | \
  60                                         FTIM0_NOR_TAVDS(0x0) | \
  61                                         FTIM0_NOR_TEAHC(0xc))
  62 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1c) | \
  63                                         FTIM1_NOR_TRAD_NOR(0xb) | \
  64                                         FTIM1_NOR_TSEQRAD_NOR(0x9))
  65 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
  66                                         FTIM2_NOR_TCH(0x4) | \
  67                                         FTIM2_NOR_TWPH(0x8) | \
  68                                         FTIM2_NOR_TWP(0x10))
  69 #define CONFIG_SYS_NOR_FTIM3            0
  70 #define CONFIG_SYS_IFC_CCR              0x01000000
  71
  72 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  73 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  74 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  75 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  76
  77 #define CONFIG_SYS_FLASH_EMPTY_INFO
  78 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  79
  80 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  81 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  82
  83 /*
  84  * NAND Flash Definitions
  85  */
  86 #ifndef SPL_NO_IFC
  87 #define CONFIG_NAND_FSL_IFC
  88 #endif
  89
  90 #define CONFIG_SYS_NAND_BASE            0x7e800000
  91 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  92
  93 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  94 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  95                                 | CSPR_PORT_SIZE_8      \
  96                                 | CSPR_MSEL_NAND        \
  97                                 | CSPR_V)
  98 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
  99 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 100                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 101                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 102                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 103                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 104                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 105                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 106
 107 #define CONFIG_SYS_NAND_ONFI_DETECTION
 108
 109 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 110                                         FTIM0_NAND_TWP(0x18)   | \
 111                                         FTIM0_NAND_TWCHT(0x7) | \
 112                                         FTIM0_NAND_TWH(0xa))
 113 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 114                                         FTIM1_NAND_TWBE(0x39)  | \
 115                                         FTIM1_NAND_TRR(0xe)   | \
 116                                         FTIM1_NAND_TRP(0x18))
 117 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 118                                         FTIM2_NAND_TREH(0xa) | \
 119                                         FTIM2_NAND_TWHRE(0x1e))
 120 #define CONFIG_SYS_NAND_FTIM3           0x0
 121
 122 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 123 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 124 #define CONFIG_MTD_NAND_VERIFY_WRITE
 125
 126 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 127
 128 #ifdef CONFIG_NAND_BOOT
 129 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
 130 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 131 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (1024 << 10)
 132 #endif
 133
 134 /*
 135  * CPLD
 136  */
 137 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
 138 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
 139
 140 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
 141 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 142                                         CSPR_PORT_SIZE_8 | \
 143                                         CSPR_MSEL_GPCM | \
 144                                         CSPR_V)
 145 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
 146 #define CONFIG_SYS_CPLD_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 147                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 148                                         CSOR_NOR_TRHZ_80)
 149
 150 /* CPLD Timing parameters for IFC GPCM */
 151 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 152                                         FTIM0_GPCM_TEADC(0xf) | \
 153                                         FTIM0_GPCM_TEAHC(0xf))
 154 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 155                                         FTIM1_GPCM_TRAD(0x3f))
 156 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 157                                         FTIM2_GPCM_TCH(0xf) | \
 158                                         FTIM2_GPCM_TWP(0xff))
 159 #define CONFIG_SYS_CPLD_FTIM3           0x0
 160
 161 /* IFC Timing Params */
 162 #ifdef CONFIG_TFABOOT
 163 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 164 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 165 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 166 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 167 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 168 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 169 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 170 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 171
 172 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 173 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 174 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 175 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 176 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 177 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 178 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 179 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 180 #else
 181 #ifdef CONFIG_NAND_BOOT
 182 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 183 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 184 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 185 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 186 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 187 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 188 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 189 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 190
 191 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 192 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 193 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 194 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 195 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 196 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 197 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 198 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 199 #else
 200 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 201 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 202 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 203 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 204 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 205 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 206 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 207 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 208
 209 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 210 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 211 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 212 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 213 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 214 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 215 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 216 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 217 #endif
 218 #endif
 219
 220 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
 221 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
 222 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 223 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 224 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 225 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 226 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 227 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 228
 229 /* EEPROM */
 230 #ifndef SPL_NO_EEPROM
 231 #define CONFIG_ID_EEPROM
 232 #define CONFIG_SYS_I2C_EEPROM_NXID
 233 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 234 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 235 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 236 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 237 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 238 #endif
 239
 240 /*
 241  * Environment
 242  */
 243 #ifndef SPL_NO_ENV
 244 #define CONFIG_ENV_OVERWRITE
 245 #endif
 246
 247 #ifdef CONFIG_TFABOOT
 248 #define CONFIG_SYS_MMC_ENV_DEV          0
 249 #else
 250 #if defined(CONFIG_NAND_BOOT)
 251 #elif defined(CONFIG_SD_BOOT)
 252 #define CONFIG_SYS_MMC_ENV_DEV          0
 253 #endif
 254 #endif
 255
 256 /* FMan */
 257 #ifndef SPL_NO_FMAN
 258 #define AQR105_IRQ_MASK                 0x40000000
 259
 260 #ifdef CONFIG_SYS_DPAA_FMAN
 261 #define RGMII_PHY1_ADDR                 0x1
 262 #define RGMII_PHY2_ADDR                 0x2
 263
 264 #define QSGMII_PORT1_PHY_ADDR           0x4
 265 #define QSGMII_PORT2_PHY_ADDR           0x5
 266 #define QSGMII_PORT3_PHY_ADDR           0x6
 267 #define QSGMII_PORT4_PHY_ADDR           0x7
 268
 269 #define FM1_10GEC1_PHY_ADDR             0x1
 270
 271 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
 272 #endif
 273 #endif
 274
 275 /* SATA */
 276 #ifndef SPL_NO_SATA
 277 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             2
 278 #define CONFIG_SYS_SCSI_MAX_LUN                 2
 279 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 280                                                 CONFIG_SYS_SCSI_MAX_LUN)
 281 #define SCSI_VEND_ID 0x1b4b
 282 #define SCSI_DEV_ID  0x9170
 283 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
 284 #endif
 285
 286 #include <asm/fsl_secure_boot.h>
 287
 288 #endif /* __LS1043ARDB_H__ */