include/configs/ls1043ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015 Freescale Semiconductor
   4  */
   5
   6 #ifndef __LS1043ARDB_H__
   7 #define __LS1043ARDB_H__
   8
   9 #include "ls1043a_common.h"
  10
  11 #define CONFIG_LAYERSCAPE_NS_ACCESS
  12
  13 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  14 /* Physical Memory Map */
  15 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  16
  17 #define CONFIG_SYS_SPD_BUS_NUM          0
  18
  19 #ifndef CONFIG_SPL
  20 #define CONFIG_SYS_DDR_RAW_TIMING
  21 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  22 #endif
  23
  24 #ifdef CONFIG_SD_BOOT
  25 #define CONFIG_SYS_SPL_ARGS_ADDR        0x90000000
  26 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR   0x500
  27 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS  30
  28 #endif
  29
  30 /*
  31  * NOR Flash Definitions
  32  */
  33 #define CONFIG_SYS_NOR_CSPR_EXT         (0x0)
  34 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  35 #define CONFIG_SYS_NOR_CSPR                                     \
  36         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  37         CSPR_PORT_SIZE_16                                       | \
  38         CSPR_MSEL_NOR                                           | \
  39         CSPR_V)
  40
  41 /* NOR Flash Timing Params */
  42 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  43                                         CSOR_NOR_TRHZ_80)
  44 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
  45                                         FTIM0_NOR_TEADC(0x1) | \
  46                                         FTIM0_NOR_TAVDS(0x0) | \
  47                                         FTIM0_NOR_TEAHC(0xc))
  48 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1c) | \
  49                                         FTIM1_NOR_TRAD_NOR(0xb) | \
  50                                         FTIM1_NOR_TSEQRAD_NOR(0x9))
  51 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
  52                                         FTIM2_NOR_TCH(0x4) | \
  53                                         FTIM2_NOR_TWPH(0x8) | \
  54                                         FTIM2_NOR_TWP(0x10))
  55 #define CONFIG_SYS_NOR_FTIM3            0
  56 #define CONFIG_SYS_IFC_CCR              0x01000000
  57
  58 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  59 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  60 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  61 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  62
  63 #define CONFIG_SYS_FLASH_EMPTY_INFO
  64 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  65
  66 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  67 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  68
  69 /*
  70  * NAND Flash Definitions
  71  */
  72
  73 #define CONFIG_SYS_NAND_BASE            0x7e800000
  74 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  75
  76 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  77 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  78                                 | CSPR_PORT_SIZE_8      \
  79                                 | CSPR_MSEL_NAND        \
  80                                 | CSPR_V)
  81 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
  82 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  83                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  84                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  85                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  86                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  87                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
  88                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  89
  90 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
  91                                         FTIM0_NAND_TWP(0x18)   | \
  92                                         FTIM0_NAND_TWCHT(0x7) | \
  93                                         FTIM0_NAND_TWH(0xa))
  94 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  95                                         FTIM1_NAND_TWBE(0x39)  | \
  96                                         FTIM1_NAND_TRR(0xe)   | \
  97                                         FTIM1_NAND_TRP(0x18))
  98 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
  99                                         FTIM2_NAND_TREH(0xa) | \
 100                                         FTIM2_NAND_TWHRE(0x1e))
 101 #define CONFIG_SYS_NAND_FTIM3           0x0
 102
 103 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 104 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 105 #define CONFIG_MTD_NAND_VERIFY_WRITE
 106
 107 #ifdef CONFIG_NAND_BOOT
 108 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
 109 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (1024 << 10)
 110 #endif
 111
 112 /*
 113  * CPLD
 114  */
 115 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
 116 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
 117
 118 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
 119 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 120                                         CSPR_PORT_SIZE_8 | \
 121                                         CSPR_MSEL_GPCM | \
 122                                         CSPR_V)
 123 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
 124 #define CONFIG_SYS_CPLD_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 125                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 126                                         CSOR_NOR_TRHZ_80)
 127
 128 /* CPLD Timing parameters for IFC GPCM */
 129 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 130                                         FTIM0_GPCM_TEADC(0xf) | \
 131                                         FTIM0_GPCM_TEAHC(0xf))
 132 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 133                                         FTIM1_GPCM_TRAD(0x3f))
 134 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 135                                         FTIM2_GPCM_TCH(0xf) | \
 136                                         FTIM2_GPCM_TWP(0xff))
 137 #define CONFIG_SYS_CPLD_FTIM3           0x0
 138
 139 /* IFC Timing Params */
 140 #ifdef CONFIG_TFABOOT
 141 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 142 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 143 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 144 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 145 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 146 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 147 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 148 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 149
 150 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 151 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 152 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 153 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 154 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 155 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 156 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 157 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 158 #else
 159 #ifdef CONFIG_NAND_BOOT
 160 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 161 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 162 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 163 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 164 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 165 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 166 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 167 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 168
 169 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 170 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 171 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 172 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 173 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 174 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 175 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 176 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 177 #else
 178 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 179 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 180 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 181 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 182 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 183 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 184 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 185 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 186
 187 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 188 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 189 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 190 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 191 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 192 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 193 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 194 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 195 #endif
 196 #endif
 197
 198 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
 199 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
 200 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 201 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 202 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 203 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 204 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 205 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 206
 207 /* EEPROM */
 208 #ifndef SPL_NO_EEPROM
 209 #define CONFIG_SYS_I2C_EEPROM_NXID
 210 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 211 #endif
 212
 213 /*
 214  * Environment
 215  */
 216
 217 /* FMan */
 218 #ifndef SPL_NO_FMAN
 219 #define AQR105_IRQ_MASK                 0x40000000
 220
 221 #ifdef CONFIG_SYS_DPAA_FMAN
 222 #define RGMII_PHY1_ADDR                 0x1
 223 #define RGMII_PHY2_ADDR                 0x2
 224
 225 #define QSGMII_PORT1_PHY_ADDR           0x4
 226 #define QSGMII_PORT2_PHY_ADDR           0x5
 227 #define QSGMII_PORT3_PHY_ADDR           0x6
 228 #define QSGMII_PORT4_PHY_ADDR           0x7
 229
 230 #define FM1_10GEC1_PHY_ADDR             0x1
 231
 232 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
 233 #endif
 234 #endif
 235
 236 /* SATA */
 237 #ifndef SPL_NO_SATA
 238 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             2
 239 #define CONFIG_SYS_SCSI_MAX_LUN                 2
 240 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 241                                                 CONFIG_SYS_SCSI_MAX_LUN)
 242 #define SCSI_VEND_ID 0x1b4b
 243 #define SCSI_DEV_ID  0x9170
 244 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
 245 #endif
 246
 247 #include <asm/fsl_secure_boot.h>
 248
 249 #endif /* __LS1043ARDB_H__ */