include/configs/ls1043ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015 Freescale Semiconductor
   4  */
   5
   6 #ifndef __LS1043ARDB_H__
   7 #define __LS1043ARDB_H__
   8
   9 #include "ls1043a_common.h"
  10
  11 /* Physical Memory Map */
  12
  13 #ifndef CONFIG_SPL
  14 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  15 #endif
  16
  17 /*
  18  * NOR Flash Definitions
  19  */
  20 #define CONFIG_SYS_NOR_CSPR_EXT         (0x0)
  21 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  22 #define CONFIG_SYS_NOR_CSPR                                     \
  23         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  24         CSPR_PORT_SIZE_16                                       | \
  25         CSPR_MSEL_NOR                                           | \
  26         CSPR_V)
  27
  28 /* NOR Flash Timing Params */
  29 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  30                                         CSOR_NOR_TRHZ_80)
  31 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x1) | \
  32                                         FTIM0_NOR_TEADC(0x1) | \
  33                                         FTIM0_NOR_TAVDS(0x0) | \
  34                                         FTIM0_NOR_TEAHC(0xc))
  35 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x1c) | \
  36                                         FTIM1_NOR_TRAD_NOR(0xb) | \
  37                                         FTIM1_NOR_TSEQRAD_NOR(0x9))
  38 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x1) | \
  39                                         FTIM2_NOR_TCH(0x4) | \
  40                                         FTIM2_NOR_TWPH(0x8) | \
  41                                         FTIM2_NOR_TWP(0x10))
  42 #define CONFIG_SYS_NOR_FTIM3            0
  43 #define CONFIG_SYS_IFC_CCR              0x01000000
  44
  45 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  46 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  47 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  48
  49 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  50
  51 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  52
  53 /*
  54  * NAND Flash Definitions
  55  */
  56
  57 #define CONFIG_SYS_NAND_BASE            0x7e800000
  58 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  59
  60 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  61 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  62                                 | CSPR_PORT_SIZE_8      \
  63                                 | CSPR_MSEL_NAND        \
  64                                 | CSPR_V)
  65 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
  66 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  67                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  68                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  69                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  70                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  71                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
  72                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  73
  74 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
  75                                         FTIM0_NAND_TWP(0x18)   | \
  76                                         FTIM0_NAND_TWCHT(0x7) | \
  77                                         FTIM0_NAND_TWH(0xa))
  78 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  79                                         FTIM1_NAND_TWBE(0x39)  | \
  80                                         FTIM1_NAND_TRR(0xe)   | \
  81                                         FTIM1_NAND_TRP(0x18))
  82 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
  83                                         FTIM2_NAND_TREH(0xa) | \
  84                                         FTIM2_NAND_TWHRE(0x1e))
  85 #define CONFIG_SYS_NAND_FTIM3           0x0
  86
  87 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  88 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  89 #define CONFIG_MTD_NAND_VERIFY_WRITE
  90
  91 #ifdef CONFIG_NAND_BOOT
  92 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (1024 << 10)
  93 #endif
  94
  95 /*
  96  * CPLD
  97  */
  98 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
  99 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
 100
 101 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
 102 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 103                                         CSPR_PORT_SIZE_8 | \
 104                                         CSPR_MSEL_GPCM | \
 105                                         CSPR_V)
 106 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
 107 #define CONFIG_SYS_CPLD_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 108                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 109                                         CSOR_NOR_TRHZ_80)
 110
 111 /* CPLD Timing parameters for IFC GPCM */
 112 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 113                                         FTIM0_GPCM_TEADC(0xf) | \
 114                                         FTIM0_GPCM_TEAHC(0xf))
 115 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 116                                         FTIM1_GPCM_TRAD(0x3f))
 117 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 118                                         FTIM2_GPCM_TCH(0xf) | \
 119                                         FTIM2_GPCM_TWP(0xff))
 120 #define CONFIG_SYS_CPLD_FTIM3           0x0
 121
 122 /* IFC Timing Params */
 123 #ifdef CONFIG_TFABOOT
 124 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 125 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 126 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 127 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 128 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 129 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 130 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 131 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 132
 133 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 134 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 135 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 136 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 137 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 138 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 139 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 140 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 141 #else
 142 #ifdef CONFIG_NAND_BOOT
 143 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 144 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 145 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 146 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 147 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 148 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 149 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 150 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 151
 152 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR_CSPR_EXT
 153 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 154 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 155 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 156 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 157 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 158 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 159 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 160 #else
 161 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
 162 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 163 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 164 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 165 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 166 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 167 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 168 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 169
 170 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 171 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 172 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 173 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 174 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 175 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 176 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 177 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 178 #endif
 179 #endif
 180
 181 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
 182 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
 183 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 184 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 185 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 186 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 187 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 188 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 189
 190 /* EEPROM */
 191 #ifndef SPL_NO_EEPROM
 192 #define CONFIG_SYS_I2C_EEPROM_NXID
 193 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 194 #endif
 195
 196 /*
 197  * Environment
 198  */
 199
 200 /* FMan */
 201 #ifndef SPL_NO_FMAN
 202 #define AQR105_IRQ_MASK                 0x40000000
 203
 204 #ifdef CONFIG_SYS_DPAA_FMAN
 205 #define RGMII_PHY1_ADDR                 0x1
 206 #define RGMII_PHY2_ADDR                 0x2
 207
 208 #define QSGMII_PORT1_PHY_ADDR           0x4
 209 #define QSGMII_PORT2_PHY_ADDR           0x5
 210 #define QSGMII_PORT3_PHY_ADDR           0x6
 211 #define QSGMII_PORT4_PHY_ADDR           0x7
 212
 213 #define FM1_10GEC1_PHY_ADDR             0x1
 214 #endif
 215 #endif
 216
 217 /* SATA */
 218 #ifndef SPL_NO_SATA
 219 #define SCSI_VEND_ID 0x1b4b
 220 #define SCSI_DEV_ID  0x9170
 221 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
 222 #endif
 223
 224 #include <asm/fsl_secure_boot.h>
 225
 226 #endif /* __LS1043ARDB_H__ */