1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor, Inc.
6 #ifndef __LS1043AQDS_H__
7 #define __LS1043AQDS_H__
9 #include "ls1043a_common.h"
11 /* Physical Memory Map */
13 #define SPD_EEPROM_ADDRESS 0x51
16 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
19 #ifdef CONFIG_SYS_DPAA_FMAN
20 #define RGMII_PHY1_ADDR 0x1
21 #define RGMII_PHY2_ADDR 0x2
22 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
23 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
24 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
25 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
26 /* PHY address on QSGMII riser card on slot 1 */
27 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
28 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
29 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
30 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
31 /* PHY address on QSGMII riser card on slot 2 */
32 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
33 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
34 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
35 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
41 #define CONFIG_SYS_I2C_EEPROM_NXID
42 #define CONFIG_SYS_EEPROM_BUS_NUM 0
44 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
49 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
50 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
51 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
55 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
56 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
61 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
63 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
65 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
66 FTIM0_NOR_TEADC(0x5) | \
68 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
69 FTIM1_NOR_TRAD_NOR(0x1a) | \
70 FTIM1_NOR_TSEQRAD_NOR(0x13))
71 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
72 FTIM2_NOR_TCH(0x4) | \
73 FTIM2_NOR_TWPH(0xe) | \
75 #define CONFIG_SYS_NOR_FTIM3 0
77 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
79 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
80 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
82 #define CONFIG_SYS_WRITE_SWAPPED_DATA
85 * NAND Flash Definitions
88 #define CONFIG_SYS_NAND_BASE 0x7e800000
89 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
91 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
93 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
97 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
98 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
99 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
100 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
101 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
102 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
103 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
104 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
106 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
107 FTIM0_NAND_TWP(0x18) | \
108 FTIM0_NAND_TWCHT(0x7) | \
110 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
111 FTIM1_NAND_TWBE(0x39) | \
112 FTIM1_NAND_TRR(0xe) | \
113 FTIM1_NAND_TRP(0x18))
114 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
115 FTIM2_NAND_TREH(0xa) | \
116 FTIM2_NAND_TWHRE(0x1e))
117 #define CONFIG_SYS_NAND_FTIM3 0x0
119 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
120 #define CONFIG_SYS_MAX_NAND_DEVICE 1
121 #define CONFIG_MTD_NAND_VERIFY_WRITE
124 #ifdef CONFIG_NAND_BOOT
125 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
128 #if defined(CONFIG_TFABOOT) || \
129 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
136 #ifdef CONFIG_FSL_QIXIS
137 #define QIXIS_BASE 0x7fb00000
138 #define QIXIS_BASE_PHYS QIXIS_BASE
139 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
140 #define QIXIS_LBMAP_SWITCH 6
141 #define QIXIS_LBMAP_MASK 0x0f
142 #define QIXIS_LBMAP_SHIFT 0
143 #define QIXIS_LBMAP_DFLTBANK 0x00
144 #define QIXIS_LBMAP_ALTBANK 0x04
145 #define QIXIS_LBMAP_NAND 0x09
146 #define QIXIS_LBMAP_SD 0x00
147 #define QIXIS_LBMAP_SD_QSPI 0xff
148 #define QIXIS_LBMAP_QSPI 0xff
149 #define QIXIS_RCW_SRC_NAND 0x106
150 #define QIXIS_RCW_SRC_SD 0x040
151 #define QIXIS_RCW_SRC_QSPI 0x045
152 #define QIXIS_RST_CTL_RESET 0x41
153 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
154 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
155 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
157 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
158 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
162 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
163 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
164 CSOR_NOR_NOR_MODE_AVD_NOR | \
168 * QIXIS Timing parameters for IFC GPCM
170 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
171 FTIM0_GPCM_TEADC(0x20) | \
172 FTIM0_GPCM_TEAHC(0x10))
173 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
174 FTIM1_GPCM_TRAD(0x1f))
175 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
176 FTIM2_GPCM_TCH(0x8) | \
177 FTIM2_GPCM_TWP(0xf0))
178 #define CONFIG_SYS_FPGA_FTIM3 0x0
181 #ifdef CONFIG_TFABOOT
182 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
183 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
184 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
185 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
186 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
187 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
188 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
189 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
190 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
191 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
192 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
193 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
194 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
195 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
196 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
197 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
198 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
199 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
200 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
201 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
202 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
203 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
204 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
205 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
206 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
207 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
208 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
209 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
210 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
211 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
212 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
213 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
215 #ifdef CONFIG_NAND_BOOT
216 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
217 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
218 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
219 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
220 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
221 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
222 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
223 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
224 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
225 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
226 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
227 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
228 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
229 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
230 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
231 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
232 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
233 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
234 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
235 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
236 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
237 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
238 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
239 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
240 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
241 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
242 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
243 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
244 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
245 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
246 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
247 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
249 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
250 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
251 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
252 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
253 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
254 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
255 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
256 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
257 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
258 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
259 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
260 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
261 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
262 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
263 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
264 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
265 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
266 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
267 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
268 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
269 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
270 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
271 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
272 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
273 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
274 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
275 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
276 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
277 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
278 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
279 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
280 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
285 * I2C bus multiplexer
287 #define I2C_MUX_PCA_ADDR_PRI 0x77
288 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
289 #define I2C_RETIMER_ADDR 0x18
290 #define I2C_MUX_CH_DEFAULT 0x8
291 #define I2C_MUX_CH_CH7301 0xC
292 #define I2C_MUX_CH5 0xD
293 #define I2C_MUX_CH7 0xF
295 #define I2C_MUX_CH_VOL_MONITOR 0xa
297 /* Voltage monitor on channel 2*/
298 #define I2C_VOL_MONITOR_ADDR 0x40
299 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
300 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
301 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
303 /* The lowest and highest voltage allowed for LS1043AQDS */
304 #define VDD_MV_MIN 819
305 #define VDD_MV_MAX 1212
308 * Miscellaneous configurable options
315 #include <asm/fsl_secure_boot.h>
317 #endif /* __LS1043AQDS_H__ */