include/configs/ls1043aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1043AQDS_H__
   7 #define __LS1043AQDS_H__
   8
   9 #include "ls1043a_common.h"
  10
  11 #define CONFIG_LAYERSCAPE_NS_ACCESS
  12
  13 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  14 /* Physical Memory Map */
  15 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  16
  17 #define SPD_EEPROM_ADDRESS              0x51
  18 #define CONFIG_SYS_SPD_BUS_NUM          0
  19
  20 #ifdef CONFIG_DDR_ECC
  21 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  22 #endif
  23
  24 #ifdef CONFIG_SYS_DPAA_FMAN
  25 #define RGMII_PHY1_ADDR         0x1
  26 #define RGMII_PHY2_ADDR         0x2
  27 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  28 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  29 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  30 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  31 /* PHY address on QSGMII riser card on slot 1 */
  32 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
  33 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
  34 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
  35 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
  36 /* PHY address on QSGMII riser card on slot 2 */
  37 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  38 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  39 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  40 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  41 #endif
  42
  43 /* LPUART */
  44 #ifdef CONFIG_LPUART
  45 #define CONFIG_LPUART_32B_REG
  46 #endif
  47
  48 /* SATA */
  49 #define CONFIG_SCSI_AHCI_PLAT
  50
  51 /* EEPROM */
  52 #define CONFIG_SYS_I2C_EEPROM_NXID
  53 #define CONFIG_SYS_EEPROM_BUS_NUM               0
  54
  55 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
  56
  57 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  58 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  59 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  60                                                 CONFIG_SYS_SCSI_MAX_LUN)
  61
  62 /*
  63  * IFC Definitions
  64  */
  65 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  66 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  67 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  68                                 CSPR_PORT_SIZE_16 | \
  69                                 CSPR_MSEL_NOR | \
  70                                 CSPR_V)
  71 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  72 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  73                                 + 0x8000000) | \
  74                                 CSPR_PORT_SIZE_16 | \
  75                                 CSPR_MSEL_NOR | \
  76                                 CSPR_V)
  77 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  78
  79 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  80                                         CSOR_NOR_TRHZ_80)
  81 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  82                                         FTIM0_NOR_TEADC(0x5) | \
  83                                         FTIM0_NOR_TEAHC(0x5))
  84 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  85                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  86                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  87 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  88                                         FTIM2_NOR_TCH(0x4) | \
  89                                         FTIM2_NOR_TWPH(0xe) | \
  90                                         FTIM2_NOR_TWP(0x1c))
  91 #define CONFIG_SYS_NOR_FTIM3            0
  92
  93 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  94 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  95 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  96
  97 #define CONFIG_SYS_FLASH_EMPTY_INFO
  98 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
  99                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 100
 101 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 102 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 103
 104 /*
 105  * NAND Flash Definitions
 106  */
 107
 108 #define CONFIG_SYS_NAND_BASE            0x7e800000
 109 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 110
 111 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 112
 113 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 114                                 | CSPR_PORT_SIZE_8      \
 115                                 | CSPR_MSEL_NAND        \
 116                                 | CSPR_V)
 117 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 118 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 119                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 120                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 121                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 122                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 123                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 124                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 125
 126 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 127                                         FTIM0_NAND_TWP(0x18)   | \
 128                                         FTIM0_NAND_TWCHT(0x7) | \
 129                                         FTIM0_NAND_TWH(0xa))
 130 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 131                                         FTIM1_NAND_TWBE(0x39)  | \
 132                                         FTIM1_NAND_TRR(0xe)   | \
 133                                         FTIM1_NAND_TRP(0x18))
 134 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 135                                         FTIM2_NAND_TREH(0xa) | \
 136                                         FTIM2_NAND_TWHRE(0x1e))
 137 #define CONFIG_SYS_NAND_FTIM3           0x0
 138
 139 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 140 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 141 #define CONFIG_MTD_NAND_VERIFY_WRITE
 142 #endif
 143
 144 #ifdef CONFIG_NAND_BOOT
 145 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
 146 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 << 10)
 147 #endif
 148
 149 #if defined(CONFIG_TFABOOT) || \
 150         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 151 #define CONFIG_QIXIS_I2C_ACCESS
 152 #endif
 153
 154 /*
 155  * QIXIS Definitions
 156  */
 157 #define CONFIG_FSL_QIXIS
 158
 159 #ifdef CONFIG_FSL_QIXIS
 160 #define QIXIS_BASE                      0x7fb00000
 161 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 162 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 163 #define QIXIS_LBMAP_SWITCH              6
 164 #define QIXIS_LBMAP_MASK                0x0f
 165 #define QIXIS_LBMAP_SHIFT               0
 166 #define QIXIS_LBMAP_DFLTBANK            0x00
 167 #define QIXIS_LBMAP_ALTBANK             0x04
 168 #define QIXIS_LBMAP_NAND                0x09
 169 #define QIXIS_LBMAP_SD                  0x00
 170 #define QIXIS_LBMAP_SD_QSPI             0xff
 171 #define QIXIS_LBMAP_QSPI                0xff
 172 #define QIXIS_RCW_SRC_NAND              0x106
 173 #define QIXIS_RCW_SRC_SD                0x040
 174 #define QIXIS_RCW_SRC_QSPI              0x045
 175 #define QIXIS_RST_CTL_RESET             0x41
 176 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 177 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 178 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 179
 180 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 181 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 182                                         CSPR_PORT_SIZE_8 | \
 183                                         CSPR_MSEL_GPCM | \
 184                                         CSPR_V)
 185 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 186 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 187                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 188                                         CSOR_NOR_TRHZ_80)
 189
 190 /*
 191  * QIXIS Timing parameters for IFC GPCM
 192  */
 193 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 194                                         FTIM0_GPCM_TEADC(0x20) | \
 195                                         FTIM0_GPCM_TEAHC(0x10))
 196 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 197                                         FTIM1_GPCM_TRAD(0x1f))
 198 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 199                                         FTIM2_GPCM_TCH(0x8) | \
 200                                         FTIM2_GPCM_TWP(0xf0))
 201 #define CONFIG_SYS_FPGA_FTIM3           0x0
 202 #endif
 203
 204 #ifdef CONFIG_TFABOOT
 205 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 206 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 207 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 208 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 209 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 210 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 211 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 212 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 213 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 214 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 215 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 216 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 217 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 218 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 219 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 220 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 221 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 222 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 223 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 224 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 225 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 226 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 227 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 228 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 229 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 230 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 231 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 232 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 233 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 234 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 235 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 236 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 237 #else
 238 #ifdef CONFIG_NAND_BOOT
 239 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 240 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 241 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 242 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 243 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 244 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 245 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 246 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 247 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 248 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 249 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 250 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 251 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 252 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 253 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 254 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 255 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 256 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 257 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 258 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 259 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 260 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 261 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 262 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 263 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 264 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 265 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 266 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 267 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 268 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 269 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 270 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 271 #else
 272 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 273 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 274 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 275 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 276 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 277 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 278 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 279 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 280 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 281 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 282 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 283 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 284 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 285 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 286 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 287 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 288 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 289 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 290 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 291 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 292 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 293 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 294 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 295 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 296 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 297 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 298 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 299 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 300 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 301 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 302 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 303 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 304 #endif
 305 #endif
 306
 307 /*
 308  * I2C bus multiplexer
 309  */
 310 #define I2C_MUX_PCA_ADDR_PRI            0x77
 311 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 312 #define I2C_RETIMER_ADDR                0x18
 313 #define I2C_MUX_CH_DEFAULT              0x8
 314 #define I2C_MUX_CH_CH7301               0xC
 315 #define I2C_MUX_CH5                     0xD
 316 #define I2C_MUX_CH7                     0xF
 317
 318 #define I2C_MUX_CH_VOL_MONITOR 0xa
 319
 320 /* Voltage monitor on channel 2*/
 321 #define I2C_VOL_MONITOR_ADDR           0x40
 322 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 323 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 324 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 325
 326 /* The lowest and highest voltage allowed for LS1043AQDS */
 327 #define VDD_MV_MIN                      819
 328 #define VDD_MV_MAX                      1212
 329
 330 /*
 331  * Miscellaneous configurable options
 332  */
 333
 334 #define CONFIG_SYS_INIT_SP_OFFSET \
 335         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 336
 337 #ifdef CONFIG_SPL_BUILD
 338 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 339 #else
 340 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 341 #endif
 342
 343 /*
 344  * Environment
 345  */
 346
 347 #include <asm/fsl_secure_boot.h>
 348
 349 #endif /* __LS1043AQDS_H__ */