include/configs/ls1043aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __LS1043AQDS_H__
   7 #define __LS1043AQDS_H__
   8
   9 #include "ls1043a_common.h"
  10
  11 /* Physical Memory Map */
  12
  13 #define SPD_EEPROM_ADDRESS              0x51
  14
  15 #ifdef CONFIG_DDR_ECC
  16 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  17 #endif
  18
  19 #ifdef CONFIG_SYS_DPAA_FMAN
  20 #define RGMII_PHY1_ADDR         0x1
  21 #define RGMII_PHY2_ADDR         0x2
  22 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  23 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  24 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  25 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  26 /* PHY address on QSGMII riser card on slot 1 */
  27 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
  28 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
  29 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
  30 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
  31 /* PHY address on QSGMII riser card on slot 2 */
  32 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  33 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  34 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  35 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  36 #endif
  37
  38 /* SATA */
  39
  40 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
  41
  42 /*
  43  * IFC Definitions
  44  */
  45 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  46 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  47 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  48                                 CSPR_PORT_SIZE_16 | \
  49                                 CSPR_MSEL_NOR | \
  50                                 CSPR_V)
  51 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  52 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  53                                 + 0x8000000) | \
  54                                 CSPR_PORT_SIZE_16 | \
  55                                 CSPR_MSEL_NOR | \
  56                                 CSPR_V)
  57 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  58
  59 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  60                                         CSOR_NOR_TRHZ_80)
  61 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  62                                         FTIM0_NOR_TEADC(0x5) | \
  63                                         FTIM0_NOR_TEAHC(0x5))
  64 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  65                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  66                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  67 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  68                                         FTIM2_NOR_TCH(0x4) | \
  69                                         FTIM2_NOR_TWPH(0xe) | \
  70                                         FTIM2_NOR_TWP(0x1c))
  71 #define CONFIG_SYS_NOR_FTIM3            0
  72
  73 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
  74                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  75
  76 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  77
  78 /*
  79  * NAND Flash Definitions
  80  */
  81
  82 #define CFG_SYS_NAND_BASE               0x7e800000
  83 #define CFG_SYS_NAND_BASE_PHYS  CFG_SYS_NAND_BASE
  84
  85 #define CFG_SYS_NAND_CSPR_EXT   (0x0)
  86
  87 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
  88                                 | CSPR_PORT_SIZE_8      \
  89                                 | CSPR_MSEL_NAND        \
  90                                 | CSPR_V)
  91 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
  92 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  93                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  94                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  95                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  96                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  97                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
  98                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  99
 100 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x7) | \
 101                                         FTIM0_NAND_TWP(0x18)   | \
 102                                         FTIM0_NAND_TWCHT(0x7) | \
 103                                         FTIM0_NAND_TWH(0xa))
 104 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
 105                                         FTIM1_NAND_TWBE(0x39)  | \
 106                                         FTIM1_NAND_TRR(0xe)   | \
 107                                         FTIM1_NAND_TRP(0x18))
 108 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0xf) | \
 109                                         FTIM2_NAND_TREH(0xa) | \
 110                                         FTIM2_NAND_TWHRE(0x1e))
 111 #define CFG_SYS_NAND_FTIM3           0x0
 112
 113 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 114 #define CONFIG_MTD_NAND_VERIFY_WRITE
 115 #endif
 116
 117 #ifdef CONFIG_NAND_BOOT
 118 #define CFG_SYS_NAND_U_BOOT_SIZE        (640 << 10)
 119 #endif
 120
 121 #if defined(CONFIG_TFABOOT) || \
 122         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 123 #endif
 124
 125 /*
 126  * QIXIS Definitions
 127  */
 128
 129 #ifdef CONFIG_FSL_QIXIS
 130 #define QIXIS_BASE                      0x7fb00000
 131 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 132 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 133 #define QIXIS_LBMAP_SWITCH              6
 134 #define QIXIS_LBMAP_MASK                0x0f
 135 #define QIXIS_LBMAP_SHIFT               0
 136 #define QIXIS_LBMAP_DFLTBANK            0x00
 137 #define QIXIS_LBMAP_ALTBANK             0x04
 138 #define QIXIS_LBMAP_NAND                0x09
 139 #define QIXIS_LBMAP_SD                  0x00
 140 #define QIXIS_LBMAP_SD_QSPI             0xff
 141 #define QIXIS_LBMAP_QSPI                0xff
 142 #define QIXIS_RCW_SRC_NAND              0x106
 143 #define QIXIS_RCW_SRC_SD                0x040
 144 #define QIXIS_RCW_SRC_QSPI              0x045
 145 #define QIXIS_RST_CTL_RESET             0x41
 146 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 147 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 148 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 149
 150 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 151 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 152                                         CSPR_PORT_SIZE_8 | \
 153                                         CSPR_MSEL_GPCM | \
 154                                         CSPR_V)
 155 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 156 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 157                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 158                                         CSOR_NOR_TRHZ_80)
 159
 160 /*
 161  * QIXIS Timing parameters for IFC GPCM
 162  */
 163 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 164                                         FTIM0_GPCM_TEADC(0x20) | \
 165                                         FTIM0_GPCM_TEAHC(0x10))
 166 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 167                                         FTIM1_GPCM_TRAD(0x1f))
 168 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 169                                         FTIM2_GPCM_TCH(0x8) | \
 170                                         FTIM2_GPCM_TWP(0xf0))
 171 #define CONFIG_SYS_FPGA_FTIM3           0x0
 172 #endif
 173
 174 #ifdef CONFIG_TFABOOT
 175 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 176 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 177 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 178 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 179 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 180 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 181 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 182 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 183 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 184 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 185 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 186 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 187 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 188 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 189 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 190 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 191 #define CONFIG_SYS_CSPR2_EXT            CFG_SYS_NAND_CSPR_EXT
 192 #define CONFIG_SYS_CSPR2                CFG_SYS_NAND_CSPR
 193 #define CONFIG_SYS_AMASK2               CFG_SYS_NAND_AMASK
 194 #define CONFIG_SYS_CSOR2                CFG_SYS_NAND_CSOR
 195 #define CONFIG_SYS_CS2_FTIM0            CFG_SYS_NAND_FTIM0
 196 #define CONFIG_SYS_CS2_FTIM1            CFG_SYS_NAND_FTIM1
 197 #define CONFIG_SYS_CS2_FTIM2            CFG_SYS_NAND_FTIM2
 198 #define CONFIG_SYS_CS2_FTIM3            CFG_SYS_NAND_FTIM3
 199 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 200 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 201 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 202 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 203 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 204 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 205 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 206 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 207 #else
 208 #ifdef CONFIG_NAND_BOOT
 209 #define CONFIG_SYS_CSPR0_EXT            CFG_SYS_NAND_CSPR_EXT
 210 #define CONFIG_SYS_CSPR0                CFG_SYS_NAND_CSPR
 211 #define CONFIG_SYS_AMASK0               CFG_SYS_NAND_AMASK
 212 #define CONFIG_SYS_CSOR0                CFG_SYS_NAND_CSOR
 213 #define CONFIG_SYS_CS0_FTIM0            CFG_SYS_NAND_FTIM0
 214 #define CONFIG_SYS_CS0_FTIM1            CFG_SYS_NAND_FTIM1
 215 #define CONFIG_SYS_CS0_FTIM2            CFG_SYS_NAND_FTIM2
 216 #define CONFIG_SYS_CS0_FTIM3            CFG_SYS_NAND_FTIM3
 217 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 218 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 219 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 220 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 221 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 222 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 223 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 224 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 225 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 226 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 227 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 228 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 229 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 230 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 231 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 232 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 233 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 234 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 235 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 236 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 237 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 238 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 239 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 240 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 241 #else
 242 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 243 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 244 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 245 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 246 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 247 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 248 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 249 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 250 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 251 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 252 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 253 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 254 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 255 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 256 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 257 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 258 #define CONFIG_SYS_CSPR2_EXT            CFG_SYS_NAND_CSPR_EXT
 259 #define CONFIG_SYS_CSPR2                CFG_SYS_NAND_CSPR
 260 #define CONFIG_SYS_AMASK2               CFG_SYS_NAND_AMASK
 261 #define CONFIG_SYS_CSOR2                CFG_SYS_NAND_CSOR
 262 #define CONFIG_SYS_CS2_FTIM0            CFG_SYS_NAND_FTIM0
 263 #define CONFIG_SYS_CS2_FTIM1            CFG_SYS_NAND_FTIM1
 264 #define CONFIG_SYS_CS2_FTIM2            CFG_SYS_NAND_FTIM2
 265 #define CONFIG_SYS_CS2_FTIM3            CFG_SYS_NAND_FTIM3
 266 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 267 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 268 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 269 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 270 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 271 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 272 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 273 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 274 #endif
 275 #endif
 276
 277 /*
 278  * I2C bus multiplexer
 279  */
 280 #define I2C_MUX_PCA_ADDR_PRI            0x77
 281 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 282 #define I2C_RETIMER_ADDR                0x18
 283 #define I2C_MUX_CH_DEFAULT              0x8
 284 #define I2C_MUX_CH_CH7301               0xC
 285 #define I2C_MUX_CH5                     0xD
 286 #define I2C_MUX_CH7                     0xF
 287
 288 #define I2C_MUX_CH_VOL_MONITOR 0xa
 289
 290 /* Voltage monitor on channel 2*/
 291 #define I2C_VOL_MONITOR_ADDR           0x40
 292 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 293 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 294 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 295
 296 /* The lowest and highest voltage allowed for LS1043AQDS */
 297 #define VDD_MV_MIN                      819
 298 #define VDD_MV_MAX                      1212
 299
 300 /*
 301  * Miscellaneous configurable options
 302  */
 303
 304 /*
 305  * Environment
 306  */
 307
 308 #include <asm/fsl_secure_boot.h>
 309
 310 #endif /* __LS1043AQDS_H__ */