include/configs/ls1043a_common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2015 Freescale Semiconductor
   4  * Copyright 2019-2021 NXP
   5  */
   6
   7 #ifndef __LS1043A_COMMON_H
   8 #define __LS1043A_COMMON_H
   9
  10 /* SPL build */
  11 #ifdef CONFIG_SPL_BUILD
  12 #define SPL_NO_FMAN
  13 #define SPL_NO_DSPI
  14 #define SPL_NO_PCIE
  15 #define SPL_NO_ENV
  16 #define SPL_NO_MISC
  17 #define SPL_NO_USB
  18 #define SPL_NO_SATA
  19 #define SPL_NO_QE
  20 #define SPL_NO_EEPROM
  21 #endif
  22 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
  23 #define SPL_NO_MMC
  24 #endif
  25 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
  26 #define SPL_NO_IFC
  27 #endif
  28
  29 #define CONFIG_REMAKE_ELF
  30
  31 #include <asm/arch/stream_id_lsch2.h>
  32 #include <asm/arch/config.h>
  33
  34 /* Link Definitions */
  35 #ifdef CONFIG_TFABOOT
  36 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SYS_TEXT_BASE
  37 #else
  38 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  39 #endif
  40
  41 #define CONFIG_VERY_BIG_RAM
  42 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
  43 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  44 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  45 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
  46
  47 #define CPU_RELEASE_ADDR               secondary_boot_addr
  48
  49 /* Generic Timer Definitions */
  50 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  51
  52 /* Serial Port */
  53 #define CONFIG_SYS_NS16550_SERIAL
  54 #define CONFIG_SYS_NS16550_REG_SIZE     1
  55 #define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
  56
  57 /* SD boot SPL */
  58 #ifdef CONFIG_SD_BOOT
  59
  60 #define CONFIG_SPL_MAX_SIZE             0x17000
  61 #define CONFIG_SPL_STACK                0x1001e000
  62 #define CONFIG_SPL_PAD_TO               0x1d000
  63
  64 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
  65                                         CONFIG_SPL_BSS_MAX_SIZE)
  66 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  67 #define CONFIG_SPL_BSS_START_ADDR       0x8f000000
  68 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  69
  70 #ifdef CONFIG_NXP_ESBC
  71 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  72 /*
  73  * HDR would be appended at end of image and copied to DDR along
  74  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  75  * size increases then increase this size in case of secure boot as
  76  * it uses raw u-boot image instead of fit image.
  77  */
  78 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  79 #else
  80 #define CONFIG_SYS_MONITOR_LEN          0x100000
  81 #endif /* ifdef CONFIG_NXP_ESBC */
  82 #endif
  83
  84 /* NAND SPL */
  85 #ifdef CONFIG_NAND_BOOT
  86 #define CONFIG_SPL_PBL_PAD
  87 #define CONFIG_SPL_MAX_SIZE             0x1a000
  88 #define CONFIG_SPL_STACK                0x1001d000
  89 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  90 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  91 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  92 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  93 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  94 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  95
  96 #ifdef CONFIG_NXP_ESBC
  97 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  98 #endif /* ifdef CONFIG_NXP_ESBC */
  99
 100 #ifdef CONFIG_U_BOOT_HDR_SIZE
 101 /*
 102  * HDR would be appended at end of image and copied to DDR along
 103  * with U-Boot image. Here u-boot max. size is 512K. So if binary
 104  * size increases then increase this size in case of secure boot as
 105  * it uses raw u-boot image instead of fit image.
 106  */
 107 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
 108 #else
 109 #define CONFIG_SYS_MONITOR_LEN          0x100000
 110 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
 111
 112 #endif
 113
 114 /* GPIO */
 115 #ifdef CONFIG_DM_GPIO
 116 #ifndef CONFIG_MPC8XXX_GPIO
 117 #define CONFIG_MPC8XXX_GPIO
 118 #endif
 119 #endif
 120
 121 /* IFC */
 122 #ifndef SPL_NO_IFC
 123 #if defined(CONFIG_TFABOOT) || \
 124         (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
 125 /*
 126  * CONFIG_SYS_FLASH_BASE has the final address (core view)
 127  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 128  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 129  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 130  */
 131 #define CONFIG_SYS_FLASH_BASE                   0x60000000
 132 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
 133 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 134
 135 #ifdef CONFIG_MTD_NOR_FLASH
 136 #define CONFIG_SYS_FLASH_QUIET_TEST
 137 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 138 #endif
 139 #endif
 140 #endif
 141
 142 /* I2C */
 143
 144 /* PCIe */
 145 #ifndef SPL_NO_PCIE
 146 #define CONFIG_PCIE1            /* PCIE controller 1 */
 147 #define CONFIG_PCIE2            /* PCIE controller 2 */
 148 #define CONFIG_PCIE3            /* PCIE controller 3 */
 149
 150 #ifdef CONFIG_PCI
 151 #define CONFIG_PCI_SCAN_SHOW
 152 #endif
 153 #endif
 154
 155 /*  DSPI  */
 156 #ifndef SPL_NO_DSPI
 157 #ifdef CONFIG_FSL_DSPI
 158 #define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
 159 #define CONFIG_SPI_FLASH_SST            /* cs1 */
 160 #define CONFIG_SPI_FLASH_EON            /* cs2 */
 161 #endif
 162 #endif
 163
 164 /* FMan ucode */
 165 #ifndef SPL_NO_FMAN
 166 #define CONFIG_SYS_DPAA_FMAN
 167 #ifdef CONFIG_SYS_DPAA_FMAN
 168 #define CONFIG_SYS_FM_MURAM_SIZE        0x60000
 169
 170 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 171 #endif
 172 #endif
 173
 174 /* Miscellaneous configurable options */
 175
 176 #define CONFIG_HWCONFIG
 177 #define HWCONFIG_BUFFER_SIZE            128
 178
 179 #ifndef SPL_NO_MISC
 180 #ifndef CONFIG_SPL_BUILD
 181 #define BOOT_TARGET_DEVICES(func) \
 182         func(MMC, mmc, 0) \
 183         func(USB, usb, 0) \
 184         func(DHCP, dhcp, na)
 185 #include <config_distro_bootcmd.h>
 186 #endif
 187
 188 /* Initial environment variables */
 189 #define CONFIG_EXTRA_ENV_SETTINGS               \
 190         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 191         "fdt_high=0xffffffffffffffff\0"         \
 192         "initrd_high=0xffffffffffffffff\0"      \
 193         "fdt_addr=0x64f00000\0"                 \
 194         "kernel_addr=0x61000000\0"              \
 195         "scriptaddr=0x80000000\0"               \
 196         "scripthdraddr=0x80080000\0"            \
 197         "fdtheader_addr_r=0x80100000\0"         \
 198         "kernelheader_addr_r=0x80200000\0"      \
 199         "kernel_addr_r=0x81000000\0"            \
 200         "kernel_start=0x1000000\0"              \
 201         "kernelheader_start=0x800000\0"         \
 202         "fdt_addr_r=0x90000000\0"               \
 203         "load_addr=0xa0000000\0"                \
 204         "kernelheader_addr=0x60600000\0"        \
 205         "kernel_size=0x2800000\0"               \
 206         "kernelheader_size=0x40000\0"           \
 207         "kernel_addr_sd=0x8000\0"               \
 208         "kernel_size_sd=0x14000\0"              \
 209         "kernelhdr_addr_sd=0x3000\0"            \
 210         "kernelhdr_size_sd=0x10\0"              \
 211         "console=ttyS0,115200\0"                \
 212         "boot_os=y\0"                           \
 213         "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"        \
 214         BOOTENV                                 \
 215         "boot_scripts=ls1043ardb_boot.scr\0"    \
 216         "boot_script_hdr=hdr_ls1043ardb_bs.out\0"       \
 217         "scan_dev_for_boot_part="               \
 218                 "part list ${devtype} ${devnum} devplist; "     \
 219                 "env exists devplist || setenv devplist 1; "    \
 220                 "for distro_bootpart in ${devplist}; do "       \
 221                         "if fstype ${devtype} "                 \
 222                                 "${devnum}:${distro_bootpart} " \
 223                                 "bootfstype; then "             \
 224                                 "run scan_dev_for_boot; "       \
 225                         "fi; "                                  \
 226                 "done\0"                        \
 227         "boot_a_script="                                        \
 228                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 229                         "${scriptaddr} ${prefix}${script}; "    \
 230                 "env exists secureboot && load ${devtype} "     \
 231                         "${devnum}:${distro_bootpart} "         \
 232                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 233                         "env exists secureboot "        \
 234                         "&& esbc_validate ${scripthdraddr};"    \
 235                 "source ${scriptaddr}\0"                        \
 236         "qspi_bootcmd=echo Trying load from qspi..;"    \
 237                 "sf probe && sf read $load_addr "       \
 238                 "$kernel_start $kernel_size; env exists secureboot "    \
 239                 "&& sf read $kernelheader_addr_r $kernelheader_start "  \
 240                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 241                 "bootm $load_addr#$board\0"     \
 242         "nor_bootcmd=echo Trying load from nor..;"      \
 243                 "cp.b $kernel_addr $load_addr " \
 244                 "$kernel_size; env exists secureboot "  \
 245                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
 246                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 247                 "bootm $load_addr#$board\0"         \
 248         "nand_bootcmd=echo Trying load from NAND..;"    \
 249                 "nand info; nand read $load_addr "      \
 250                 "$kernel_start $kernel_size; env exists secureboot "    \
 251                 "&& nand read $kernelheader_addr_r $kernelheader_start "        \
 252                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 253                 "bootm $load_addr#$board\0"     \
 254         "sd_bootcmd=echo Trying load from SD ..;"       \
 255                 "mmcinfo; mmc read $load_addr "         \
 256                 "$kernel_addr_sd $kernel_size_sd && "     \
 257                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
 258                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 259                 " && esbc_validate ${kernelheader_addr_r};"     \
 260                 "bootm $load_addr#$board\0"
 261
 262
 263 #ifdef CONFIG_TFABOOT
 264 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 265                            "env exists secureboot && esbc_halt;"
 266 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "  \
 267                            "env exists secureboot && esbc_halt;"
 268 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 269                            "env exists secureboot && esbc_halt;"
 270 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "   \
 271                            "env exists secureboot && esbc_halt;"
 272 #endif
 273 #endif
 274
 275 /* Monitor Command Prompt */
 276 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 277
 278 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 279
 280 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 281
 282 #include <asm/arch/soc.h>
 283
 284 #endif /* __LS1043A_COMMON_H */