Convert CONFIG_SPL_BSS_START_ADDR to Kconfig
[platform/kernel/u-boot.git] / include / configs / ls1043a_common.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2015 Freescale Semiconductor
4  * Copyright 2019-2021 NXP
5  */
6
7 #ifndef __LS1043A_COMMON_H
8 #define __LS1043A_COMMON_H
9
10 /* SPL build */
11 #ifdef CONFIG_SPL_BUILD
12 #define SPL_NO_FMAN
13 #define SPL_NO_DSPI
14 #define SPL_NO_PCIE
15 #define SPL_NO_ENV
16 #define SPL_NO_MISC
17 #define SPL_NO_USB
18 #define SPL_NO_SATA
19 #define SPL_NO_QE
20 #define SPL_NO_EEPROM
21 #endif
22 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
23 #define SPL_NO_MMC
24 #endif
25 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
26 #define SPL_NO_IFC
27 #endif
28
29 #include <asm/arch/stream_id_lsch2.h>
30 #include <asm/arch/config.h>
31
32 /* Link Definitions */
33
34 #define CONFIG_VERY_BIG_RAM
35 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
36 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
37 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
38 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
39
40 #define CPU_RELEASE_ADDR               secondary_boot_addr
41
42 /* Serial Port */
43 #define CONFIG_SYS_NS16550_SERIAL
44 #define CONFIG_SYS_NS16550_REG_SIZE     1
45 #define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
46
47 /* SD boot SPL */
48 #ifdef CONFIG_SD_BOOT
49 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
50                                         CONFIG_SPL_BSS_MAX_SIZE)
51 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
52
53 #ifdef CONFIG_NXP_ESBC
54 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
55 /*
56  * HDR would be appended at end of image and copied to DDR along
57  * with U-Boot image. Here u-boot max. size is 512K. So if binary
58  * size increases then increase this size in case of secure boot as
59  * it uses raw u-boot image instead of fit image.
60  */
61 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
62 #else
63 #define CONFIG_SYS_MONITOR_LEN          0x100000
64 #endif /* ifdef CONFIG_NXP_ESBC */
65 #endif
66
67 /* NAND SPL */
68 #ifdef CONFIG_NAND_BOOT
69 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
70 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
71 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
72 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
73
74 #ifdef CONFIG_NXP_ESBC
75 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
76 #endif /* ifdef CONFIG_NXP_ESBC */
77
78 #ifdef CONFIG_U_BOOT_HDR_SIZE
79 /*
80  * HDR would be appended at end of image and copied to DDR along
81  * with U-Boot image. Here u-boot max. size is 512K. So if binary
82  * size increases then increase this size in case of secure boot as
83  * it uses raw u-boot image instead of fit image.
84  */
85 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
86 #else
87 #define CONFIG_SYS_MONITOR_LEN          0x100000
88 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
89
90 #endif
91
92 /* GPIO */
93
94 /* IFC */
95 #ifndef SPL_NO_IFC
96 #if defined(CONFIG_TFABOOT) || \
97         (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
98 /*
99  * CONFIG_SYS_FLASH_BASE has the final address (core view)
100  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
101  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
102  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
103  */
104 #define CONFIG_SYS_FLASH_BASE                   0x60000000
105 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
106 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
107
108 #ifdef CONFIG_MTD_NOR_FLASH
109 #define CONFIG_SYS_FLASH_QUIET_TEST
110 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
111 #endif
112 #endif
113 #endif
114
115 /* I2C */
116
117 /* PCIe */
118 #ifndef SPL_NO_PCIE
119 #define CONFIG_PCIE1            /* PCIE controller 1 */
120 #define CONFIG_PCIE2            /* PCIE controller 2 */
121 #define CONFIG_PCIE3            /* PCIE controller 3 */
122
123 #ifdef CONFIG_PCI
124 #define CONFIG_PCI_SCAN_SHOW
125 #endif
126 #endif
127
128 /*  DSPI  */
129
130 /* FMan ucode */
131 #ifndef SPL_NO_FMAN
132 #define CONFIG_SYS_DPAA_FMAN
133 #ifdef CONFIG_SYS_DPAA_FMAN
134 #define CONFIG_SYS_FM_MURAM_SIZE        0x60000
135
136 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
137 #endif
138 #endif
139
140 /* Miscellaneous configurable options */
141
142 #define CONFIG_HWCONFIG
143 #define HWCONFIG_BUFFER_SIZE            128
144
145 #ifndef SPL_NO_MISC
146 #ifndef CONFIG_SPL_BUILD
147 #define BOOT_TARGET_DEVICES(func) \
148         func(MMC, mmc, 0) \
149         func(USB, usb, 0) \
150         func(DHCP, dhcp, na)
151 #include <config_distro_bootcmd.h>
152 #endif
153
154 /* Initial environment variables */
155 #define CONFIG_EXTRA_ENV_SETTINGS               \
156         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
157         "fdt_high=0xffffffffffffffff\0"         \
158         "initrd_high=0xffffffffffffffff\0"      \
159         "kernel_addr=0x61000000\0"              \
160         "scriptaddr=0x80000000\0"               \
161         "scripthdraddr=0x80080000\0"            \
162         "fdtheader_addr_r=0x80100000\0"         \
163         "kernelheader_addr_r=0x80200000\0"      \
164         "kernel_addr_r=0x81000000\0"            \
165         "kernel_start=0x1000000\0"              \
166         "kernelheader_start=0x800000\0"         \
167         "fdt_addr_r=0x90000000\0"               \
168         "load_addr=0xa0000000\0"                \
169         "kernelheader_addr=0x60600000\0"        \
170         "kernel_size=0x2800000\0"               \
171         "kernelheader_size=0x40000\0"           \
172         "kernel_addr_sd=0x8000\0"               \
173         "kernel_size_sd=0x14000\0"              \
174         "kernelhdr_addr_sd=0x3000\0"            \
175         "kernelhdr_size_sd=0x10\0"              \
176         "console=ttyS0,115200\0"                \
177         "boot_os=y\0"                           \
178         "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"        \
179         BOOTENV                                 \
180         "boot_scripts=ls1043ardb_boot.scr\0"    \
181         "boot_script_hdr=hdr_ls1043ardb_bs.out\0"       \
182         "scan_dev_for_boot_part="               \
183                 "part list ${devtype} ${devnum} devplist; "     \
184                 "env exists devplist || setenv devplist 1; "    \
185                 "for distro_bootpart in ${devplist}; do "       \
186                         "if fstype ${devtype} "                 \
187                                 "${devnum}:${distro_bootpart} " \
188                                 "bootfstype; then "             \
189                                 "run scan_dev_for_boot; "       \
190                         "fi; "                                  \
191                 "done\0"                        \
192         "boot_a_script="                                        \
193                 "load ${devtype} ${devnum}:${distro_bootpart} " \
194                         "${scriptaddr} ${prefix}${script}; "    \
195                 "env exists secureboot && load ${devtype} "     \
196                         "${devnum}:${distro_bootpart} "         \
197                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
198                         "env exists secureboot "        \
199                         "&& esbc_validate ${scripthdraddr};"    \
200                 "source ${scriptaddr}\0"                        \
201         "qspi_bootcmd=echo Trying load from qspi..;"    \
202                 "sf probe && sf read $load_addr "       \
203                 "$kernel_start $kernel_size; env exists secureboot "    \
204                 "&& sf read $kernelheader_addr_r $kernelheader_start "  \
205                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
206                 "bootm $load_addr#$board\0"     \
207         "nor_bootcmd=echo Trying load from nor..;"      \
208                 "cp.b $kernel_addr $load_addr " \
209                 "$kernel_size; env exists secureboot "  \
210                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
211                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
212                 "bootm $load_addr#$board\0"         \
213         "nand_bootcmd=echo Trying load from NAND..;"    \
214                 "nand info; nand read $load_addr "      \
215                 "$kernel_start $kernel_size; env exists secureboot "    \
216                 "&& nand read $kernelheader_addr_r $kernelheader_start "        \
217                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
218                 "bootm $load_addr#$board\0"     \
219         "sd_bootcmd=echo Trying load from SD ..;"       \
220                 "mmcinfo; mmc read $load_addr "         \
221                 "$kernel_addr_sd $kernel_size_sd && "     \
222                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
223                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
224                 " && esbc_validate ${kernelheader_addr_r};"     \
225                 "bootm $load_addr#$board\0"
226
227
228 #ifdef CONFIG_TFABOOT
229 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
230                            "env exists secureboot && esbc_halt;"
231 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "  \
232                            "env exists secureboot && esbc_halt;"
233 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
234                            "env exists secureboot && esbc_halt;"
235 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "   \
236                            "env exists secureboot && esbc_halt;"
237 #endif
238 #endif
239
240 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
241
242 #include <asm/arch/soc.h>
243
244 #endif /* __LS1043A_COMMON_H */