include/configs/ls1021atwr.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_PSCI_1_0
  11
  12 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  13
  14 #define CONFIG_SYS_FSL_CLK
  15
  16 #define CONFIG_SKIP_LOWLEVEL_INIT
  17 #define CONFIG_DEEP_SLEEP
  18
  19 /*
  20  * Size of malloc() pool
  21  */
  22 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  23
  24 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  25 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  26
  27 #define CONFIG_SYS_CLK_FREQ             100000000
  28 #define CONFIG_DDR_CLK_FREQ             100000000
  29
  30 #define DDR_SDRAM_CFG                   0x470c0008
  31 #define DDR_CS0_BNDS                    0x008000bf
  32 #define DDR_CS0_CONFIG                  0x80014302
  33 #define DDR_TIMING_CFG_0                0x50550004
  34 #define DDR_TIMING_CFG_1                0xbcb38c56
  35 #define DDR_TIMING_CFG_2                0x0040d120
  36 #define DDR_TIMING_CFG_3                0x010e1000
  37 #define DDR_TIMING_CFG_4                0x00000001
  38 #define DDR_TIMING_CFG_5                0x03401400
  39 #define DDR_SDRAM_CFG_2                 0x00401010
  40 #define DDR_SDRAM_MODE                  0x00061c60
  41 #define DDR_SDRAM_MODE_2                0x00180000
  42 #define DDR_SDRAM_INTERVAL              0x18600618
  43 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  44 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  45 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  46 #define DDR_DDR_CDR1                    0x80040000
  47 #define DDR_DDR_CDR2                    0x00000001
  48 #define DDR_SDRAM_CLK_CNTL              0x02000000
  49 #define DDR_DDR_ZQ_CNTL                 0x89080600
  50 #define DDR_CS0_CONFIG_2                0
  51 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  52 #define SDRAM_CFG2_D_INIT               0x00000010
  53 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  54 #define SDRAM_CFG2_FRC_SR               0x80000000
  55 #define SDRAM_CFG_BI                    0x00000001
  56
  57 #ifdef CONFIG_RAMBOOT_PBL
  58 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021atwr/ls102xa_pbi.cfg
  59 #endif
  60
  61 #ifdef CONFIG_SD_BOOT
  62 #ifdef CONFIG_SD_BOOT_QSPI
  63 #define CONFIG_SYS_FSL_PBL_RCW  \
  64         board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
  65 #else
  66 #define CONFIG_SYS_FSL_PBL_RCW  \
  67         board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
  68 #endif
  69 #define CONFIG_SPL_FRAMEWORK
  70
  71 #ifdef CONFIG_SECURE_BOOT
  72 /*
  73  * HDR would be appended at end of image and copied to DDR along
  74  * with U-Boot image.
  75  */
  76 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  77 #endif /* ifdef CONFIG_SECURE_BOOT */
  78
  79 #define CONFIG_SPL_TEXT_BASE            0x10000000
  80 #define CONFIG_SPL_MAX_SIZE             0x1a000
  81 #define CONFIG_SPL_STACK                0x1001d000
  82 #define CONFIG_SPL_PAD_TO               0x1c000
  83
  84 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  85                 CONFIG_SYS_MONITOR_LEN)
  86 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  87 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  88 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  89
  90 #ifdef CONFIG_U_BOOT_HDR_SIZE
  91 /*
  92  * HDR would be appended at end of image and copied to DDR along
  93  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  94  * size increases then increase this size in case of secure boot as
  95  * it uses raw u-boot image instead of fit image.
  96  */
  97 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  98 #else
  99 #define CONFIG_SYS_MONITOR_LEN          0x100000
 100 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
 101 #endif
 102
 103 #define CONFIG_NR_DRAM_BANKS            1
 104 #define PHYS_SDRAM                      0x80000000
 105 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
 106
 107 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 108 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 109
 110 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 111         !defined(CONFIG_QSPI_BOOT)
 112 #define CONFIG_U_QE
 113 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 114 #endif
 115
 116 /*
 117  * IFC Definitions
 118  */
 119 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 120 #define CONFIG_FSL_IFC
 121 #define CONFIG_SYS_FLASH_BASE           0x60000000
 122 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 123
 124 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 125 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 126                                 CSPR_PORT_SIZE_16 | \
 127                                 CSPR_MSEL_NOR | \
 128                                 CSPR_V)
 129 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 130
 131 /* NOR Flash Timing Params */
 132 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 133                                         CSOR_NOR_TRHZ_80)
 134 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 135                                         FTIM0_NOR_TEADC(0x5) | \
 136                                         FTIM0_NOR_TAVDS(0x0) | \
 137                                         FTIM0_NOR_TEAHC(0x5))
 138 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 139                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
 140                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 141 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 142                                         FTIM2_NOR_TCH(0x4) | \
 143                                         FTIM2_NOR_TWP(0x1c) | \
 144                                         FTIM2_NOR_TWPH(0x0e))
 145 #define CONFIG_SYS_NOR_FTIM3            0
 146
 147 #define CONFIG_FLASH_CFI_DRIVER
 148 #define CONFIG_SYS_FLASH_CFI
 149 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 150 #define CONFIG_SYS_FLASH_QUIET_TEST
 151 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 152
 153 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 154 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 155 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 156 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 157
 158 #define CONFIG_SYS_FLASH_EMPTY_INFO
 159 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 160
 161 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 162 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 163 #endif
 164
 165 /* CPLD */
 166
 167 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 168 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 169
 170 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 171 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 172                                         CSPR_PORT_SIZE_8 | \
 173                                         CSPR_MSEL_GPCM | \
 174                                         CSPR_V)
 175 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 176 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 177                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 178                                         CSOR_NOR_TRHZ_80)
 179
 180 /* CPLD Timing parameters for IFC GPCM */
 181 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 182                                         FTIM0_GPCM_TEADC(0xf) | \
 183                                         FTIM0_GPCM_TEAHC(0xf))
 184 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 185                                         FTIM1_GPCM_TRAD(0x3f))
 186 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 187                                         FTIM2_GPCM_TCH(0xf) | \
 188                                         FTIM2_GPCM_TWP(0xff))
 189 #define CONFIG_SYS_FPGA_FTIM3           0x0
 190 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 191 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 192 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 193 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 194 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 195 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 196 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 197 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 198 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 199 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 200 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 201 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 202 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 203 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 204 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 205 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 206
 207 /*
 208  * Serial Port
 209  */
 210 #ifdef CONFIG_LPUART
 211 #define CONFIG_LPUART_32B_REG
 212 #else
 213 #define CONFIG_CONS_INDEX               1
 214 #define CONFIG_SYS_NS16550_SERIAL
 215 #ifndef CONFIG_DM_SERIAL
 216 #define CONFIG_SYS_NS16550_REG_SIZE     1
 217 #endif
 218 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 219 #endif
 220
 221 /*
 222  * I2C
 223  */
 224 #define CONFIG_SYS_I2C
 225 #define CONFIG_SYS_I2C_MXC
 226 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 227 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 228 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 229
 230 /* EEPROM */
 231 #define CONFIG_ID_EEPROM
 232 #define CONFIG_SYS_I2C_EEPROM_NXID
 233 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 234 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 235 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 236 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 237 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 238
 239 /*
 240  * MMC
 241  */
 242 #define CONFIG_FSL_ESDHC
 243
 244 /* SPI */
 245 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 246 /* QSPI */
 247 #define QSPI0_AMBA_BASE                 0x40000000
 248 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 249 #define FSL_QSPI_FLASH_NUM              2
 250
 251 /* DSPI */
 252 #endif
 253
 254 /* DM SPI */
 255 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 256 #define CONFIG_DM_SPI_FLASH
 257 #endif
 258
 259 /*
 260  * Video
 261  */
 262 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 263 #define CONFIG_VIDEO_LOGO
 264 #define CONFIG_VIDEO_BMP_LOGO
 265
 266 #define CONFIG_FSL_DCU_SII9022A
 267 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
 268 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
 269 #endif
 270
 271 /*
 272  * eTSEC
 273  */
 274 #define CONFIG_TSEC_ENET
 275
 276 #ifdef CONFIG_TSEC_ENET
 277 #define CONFIG_MII
 278 #define CONFIG_MII_DEFAULT_TSEC         1
 279 #define CONFIG_TSEC1                    1
 280 #define CONFIG_TSEC1_NAME               "eTSEC1"
 281 #define CONFIG_TSEC2                    1
 282 #define CONFIG_TSEC2_NAME               "eTSEC2"
 283 #define CONFIG_TSEC3                    1
 284 #define CONFIG_TSEC3_NAME               "eTSEC3"
 285
 286 #define TSEC1_PHY_ADDR                  2
 287 #define TSEC2_PHY_ADDR                  0
 288 #define TSEC3_PHY_ADDR                  1
 289
 290 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 291 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 292 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 293
 294 #define TSEC1_PHYIDX                    0
 295 #define TSEC2_PHYIDX                    0
 296 #define TSEC3_PHYIDX                    0
 297
 298 #define CONFIG_ETHPRIME                 "eTSEC1"
 299
 300 #define CONFIG_PHY_ATHEROS
 301
 302 #define CONFIG_HAS_ETH0
 303 #define CONFIG_HAS_ETH1
 304 #define CONFIG_HAS_ETH2
 305 #endif
 306
 307 /* PCIe */
 308 #define CONFIG_PCIE1            /* PCIE controller 1 */
 309 #define CONFIG_PCIE2            /* PCIE controller 2 */
 310
 311 #ifdef CONFIG_PCI
 312 #define CONFIG_PCI_SCAN_SHOW
 313 #endif
 314
 315 #define CONFIG_CMDLINE_TAG
 316
 317 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 318 #define CONFIG_LAYERSCAPE_NS_ACCESS
 319 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 320 #define COUNTER_FREQUENCY               12500000
 321
 322 #define CONFIG_HWCONFIG
 323 #define HWCONFIG_BUFFER_SIZE            256
 324
 325 #define CONFIG_FSL_DEVICE_DISABLE
 326
 327 #include <config_distro_defaults.h>
 328 #define BOOT_TARGET_DEVICES(func) \
 329         func(MMC, mmc, 0) \
 330         func(USB, usb, 0)
 331 #include <config_distro_bootcmd.h>
 332
 333 #ifdef CONFIG_LPUART
 334 #define CONFIG_EXTRA_ENV_SETTINGS       \
 335         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 336         "initrd_high=0xffffffff\0"      \
 337         "fdt_high=0xffffffff\0"         \
 338         "fdt_addr=0x64f00000\0"         \
 339         "kernel_addr=0x65000000\0"      \
 340         "scriptaddr=0x80000000\0"       \
 341         "scripthdraddr=0x80080000\0"    \
 342         "fdtheader_addr_r=0x80100000\0" \
 343         "kernelheader_addr_r=0x80200000\0"      \
 344         "kernel_addr_r=0x81000000\0"    \
 345         "fdt_addr_r=0x90000000\0"       \
 346         "ramdisk_addr_r=0xa0000000\0"   \
 347         "load_addr=0xa0000000\0"        \
 348         "kernel_size=0x2800000\0"       \
 349         "kernel_addr_sd=0x8000\0"       \
 350         "kernel_size_sd=0x14000\0"      \
 351         BOOTENV                         \
 352         "boot_scripts=ls1021atwr_boot.scr\0"    \
 353         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 354                 "scan_dev_for_boot_part="       \
 355                         "part list ${devtype} ${devnum} devplist; "     \
 356                         "env exists devplist || setenv devplist 1; "    \
 357                         "for distro_bootpart in ${devplist}; do "       \
 358                         "if fstype ${devtype} "                         \
 359                                 "${devnum}:${distro_bootpart} "         \
 360                                 "bootfstype; then "                     \
 361                                 "run scan_dev_for_boot; "               \
 362                         "fi; "                  \
 363                 "done\0"                        \
 364         "scan_dev_for_boot="                              \
 365                 "echo Scanning ${devtype} "               \
 366                                 "${devnum}:${distro_bootpart}...; "  \
 367                 "for prefix in ${boot_prefixes}; do "     \
 368                         "run scan_dev_for_scripts; "      \
 369                 "done;"                                   \
 370                 "\0"                                      \
 371         "boot_a_script="                                  \
 372                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 373                         "${scriptaddr} ${prefix}${script}; "    \
 374                 "env exists secureboot && load ${devtype} "     \
 375                         "${devnum}:${distro_bootpart} "         \
 376                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 377                         "&& esbc_validate ${scripthdraddr};"    \
 378                 "source ${scriptaddr}\0"          \
 379         "installer=load mmc 0:2 $load_addr "    \
 380                 "/flex_installer_arm32.itb; "           \
 381                 "bootm $load_addr#ls1021atwr\0" \
 382         "qspi_bootcmd=echo Trying load from qspi..;"    \
 383                 "sf probe && sf read $load_addr "       \
 384                 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"        \
 385         "nor_bootcmd=echo Trying load from nor..;"      \
 386                 "cp.b $kernel_addr $load_addr "         \
 387                 "$kernel_size && bootm $load_addr#$board\0"
 388 #else
 389 #define CONFIG_EXTRA_ENV_SETTINGS       \
 390         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 391         "initrd_high=0xffffffff\0"      \
 392         "fdt_high=0xffffffff\0"         \
 393         "fdt_addr=0x64f00000\0"         \
 394         "kernel_addr=0x61000000\0"      \
 395         "kernelheader_addr=0x60800000\0"        \
 396         "scriptaddr=0x80000000\0"       \
 397         "scripthdraddr=0x80080000\0"    \
 398         "fdtheader_addr_r=0x80100000\0" \
 399         "kernelheader_addr_r=0x80200000\0"      \
 400         "kernel_addr_r=0x81000000\0"    \
 401         "kernelheader_size=0x40000\0"   \
 402         "fdt_addr_r=0x90000000\0"       \
 403         "ramdisk_addr_r=0xa0000000\0"   \
 404         "load_addr=0xa0000000\0"        \
 405         "kernel_size=0x2800000\0"       \
 406         "kernel_addr_sd=0x8000\0"       \
 407         "kernel_size_sd=0x14000\0"      \
 408         "kernelhdr_addr_sd=0x4000\0"            \
 409         "kernelhdr_size_sd=0x10\0"              \
 410         BOOTENV                         \
 411         "boot_scripts=ls1021atwr_boot.scr\0"    \
 412         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 413                 "scan_dev_for_boot_part="       \
 414                         "part list ${devtype} ${devnum} devplist; "     \
 415                         "env exists devplist || setenv devplist 1; "    \
 416                         "for distro_bootpart in ${devplist}; do "       \
 417                         "if fstype ${devtype} "                         \
 418                                 "${devnum}:${distro_bootpart} "         \
 419                                 "bootfstype; then "                     \
 420                                 "run scan_dev_for_boot; "               \
 421                         "fi; "                  \
 422                 "done\0"                        \
 423         "scan_dev_for_boot="                              \
 424                 "echo Scanning ${devtype} "               \
 425                                 "${devnum}:${distro_bootpart}...; "  \
 426                 "for prefix in ${boot_prefixes}; do "     \
 427                         "run scan_dev_for_scripts; "      \
 428                 "done;"                                   \
 429                 "\0"                                      \
 430         "boot_a_script="                                  \
 431                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 432                         "${scriptaddr} ${prefix}${script}; "    \
 433                 "env exists secureboot && load ${devtype} "     \
 434                         "${devnum}:${distro_bootpart} "         \
 435                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 436                         "&& esbc_validate ${scripthdraddr};"    \
 437                 "source ${scriptaddr}\0"          \
 438         "qspi_bootcmd=echo Trying load from qspi..;"    \
 439                 "sf probe && sf read $load_addr "       \
 440                 "$kernel_addr $kernel_size; env exists secureboot "     \
 441                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 442                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 443                 "bootm $load_addr#$board\0" \
 444         "nor_bootcmd=echo Trying load from nor..;"      \
 445                 "cp.b $kernel_addr $load_addr "         \
 446                 "$kernel_size; env exists secureboot "  \
 447                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
 448                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 449                 "bootm $load_addr#$board\0"     \
 450         "sd_bootcmd=echo Trying load from SD ..;"       \
 451                 "mmcinfo && mmc read $load_addr "       \
 452                 "$kernel_addr_sd $kernel_size_sd && "   \
 453                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
 454                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 455                 " && esbc_validate ${kernelheader_addr_r};"     \
 456                 "bootm $load_addr#$board\0"
 457 #endif
 458
 459 #undef CONFIG_BOOTCOMMAND
 460 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 461 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd"       \
 462                            "env exists secureboot && esbc_halt"
 463 #elif defined(CONFIG_SD_BOOT)
 464 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "       \
 465                            "env exists secureboot && esbc_halt;"
 466 #else
 467 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;"       \
 468                            "env exists secureboot && esbc_halt;"
 469 #endif
 470
 471 /*
 472  * Miscellaneous configurable options
 473  */
 474 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 475 #define CONFIG_AUTO_COMPLETE
 476
 477 #define CONFIG_SYS_MEMTEST_START        0x80000000
 478 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 479
 480 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 481
 482 #define CONFIG_LS102XA_STREAM_ID
 483
 484 #define CONFIG_SYS_INIT_SP_OFFSET \
 485         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 486 #define CONFIG_SYS_INIT_SP_ADDR \
 487         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 488
 489 #ifdef CONFIG_SPL_BUILD
 490 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 491 #else
 492 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 493 #endif
 494
 495 #define CONFIG_SYS_QE_FW_ADDR     0x60940000
 496
 497 /*
 498  * Environment
 499  */
 500 #define CONFIG_ENV_OVERWRITE
 501
 502 #if defined(CONFIG_SD_BOOT)
 503 #define CONFIG_ENV_OFFSET               0x300000
 504 #define CONFIG_SYS_MMC_ENV_DEV          0
 505 #define CONFIG_ENV_SIZE                 0x20000
 506 #elif defined(CONFIG_QSPI_BOOT)
 507 #define CONFIG_ENV_SIZE                 0x2000
 508 #define CONFIG_ENV_OFFSET               0x300000
 509 #define CONFIG_ENV_SECT_SIZE            0x10000
 510 #else
 511 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
 512 #define CONFIG_ENV_SIZE                 0x20000
 513 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 514 #endif
 515
 516 #define CONFIG_MISC_INIT_R
 517
 518 #include <asm/fsl_secure_boot.h>
 519 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 520
 521 #endif