1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #define CONFIG_DEEP_SLEEP
12 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
13 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
15 #define DDR_SDRAM_CFG 0x470c0008
16 #define DDR_CS0_BNDS 0x008000bf
17 #define DDR_CS0_CONFIG 0x80014302
18 #define DDR_TIMING_CFG_0 0x50550004
19 #define DDR_TIMING_CFG_1 0xbcb38c56
20 #define DDR_TIMING_CFG_2 0x0040d120
21 #define DDR_TIMING_CFG_3 0x010e1000
22 #define DDR_TIMING_CFG_4 0x00000001
23 #define DDR_TIMING_CFG_5 0x03401400
24 #define DDR_SDRAM_CFG_2 0x00401010
25 #define DDR_SDRAM_MODE 0x00061c60
26 #define DDR_SDRAM_MODE_2 0x00180000
27 #define DDR_SDRAM_INTERVAL 0x18600618
28 #define DDR_DDR_WRLVL_CNTL 0x8655f605
29 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
30 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
31 #define DDR_DDR_CDR1 0x80040000
32 #define DDR_DDR_CDR2 0x00000001
33 #define DDR_SDRAM_CLK_CNTL 0x02000000
34 #define DDR_DDR_ZQ_CNTL 0x89080600
35 #define DDR_CS0_CONFIG_2 0
36 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
37 #define SDRAM_CFG2_D_INIT 0x00000010
38 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
39 #define SDRAM_CFG2_FRC_SR 0x80000000
40 #define SDRAM_CFG_BI 0x00000001
43 #ifdef CONFIG_NXP_ESBC
45 * HDR would be appended at end of image and copied to DDR along
48 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
49 #endif /* ifdef CONFIG_NXP_ESBC */
51 #define CONFIG_SPL_MAX_SIZE 0x1a000
52 #define CONFIG_SPL_STACK 0x1001d000
53 #define CONFIG_SPL_PAD_TO 0x1c000
55 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
56 CONFIG_SYS_MONITOR_LEN)
57 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
58 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
59 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
61 #ifdef CONFIG_U_BOOT_HDR_SIZE
63 * HDR would be appended at end of image and copied to DDR along
64 * with U-Boot image. Here u-boot max. size is 512K. So if binary
65 * size increases then increase this size in case of secure boot as
66 * it uses raw u-boot image instead of fit image.
68 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
70 #define CONFIG_SYS_MONITOR_LEN 0x100000
71 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
74 #define PHYS_SDRAM 0x80000000
75 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
77 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
78 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
83 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
84 #define CONFIG_SYS_FLASH_BASE 0x60000000
85 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
87 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
88 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
92 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
94 /* NOR Flash Timing Params */
95 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
97 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
98 FTIM0_NOR_TEADC(0x5) | \
99 FTIM0_NOR_TAVDS(0x0) | \
100 FTIM0_NOR_TEAHC(0x5))
101 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
102 FTIM1_NOR_TRAD_NOR(0x1A) | \
103 FTIM1_NOR_TSEQRAD_NOR(0x13))
104 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
105 FTIM2_NOR_TCH(0x4) | \
106 FTIM2_NOR_TWP(0x1c) | \
107 FTIM2_NOR_TWPH(0x0e))
108 #define CONFIG_SYS_NOR_FTIM3 0
110 #define CONFIG_SYS_FLASH_QUIET_TEST
111 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
113 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
114 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
115 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
117 #define CONFIG_SYS_FLASH_EMPTY_INFO
118 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
120 #define CONFIG_SYS_WRITE_SWAPPED_DATA
125 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
126 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
128 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
129 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
133 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
134 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
135 CSOR_NOR_NOR_MODE_AVD_NOR | \
138 /* CPLD Timing parameters for IFC GPCM */
139 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
140 FTIM0_GPCM_TEADC(0xf) | \
141 FTIM0_GPCM_TEAHC(0xf))
142 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
143 FTIM1_GPCM_TRAD(0x3f))
144 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
145 FTIM2_GPCM_TCH(0xf) | \
146 FTIM2_GPCM_TWP(0xff))
147 #define CONFIG_SYS_FPGA_FTIM3 0x0
148 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
149 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
150 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
151 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
152 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
153 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
154 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
155 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
156 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
157 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
158 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
159 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
160 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
161 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
162 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
163 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
169 #define CONFIG_LPUART_32B_REG
171 #define CONFIG_SYS_NS16550_SERIAL
172 #ifndef CONFIG_DM_SERIAL
173 #define CONFIG_SYS_NS16550_REG_SIZE 1
175 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
185 #define CONFIG_SYS_I2C_EEPROM_NXID
186 #define CONFIG_SYS_EEPROM_BUS_NUM 1
195 #ifdef CONFIG_VIDEO_FSL_DCU_FB
196 #define CONFIG_VIDEO_BMP_LOGO
198 #define CONFIG_FSL_DCU_SII9022A
199 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
200 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
204 #define CONFIG_PCIE1 /* PCIE controller 1 */
205 #define CONFIG_PCIE2 /* PCIE controller 2 */
208 #define CONFIG_PCI_SCAN_SHOW
211 #define CONFIG_PEN_ADDR_BIG_ENDIAN
212 #define CONFIG_LAYERSCAPE_NS_ACCESS
213 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
214 #define COUNTER_FREQUENCY 12500000
216 #define CONFIG_HWCONFIG
217 #define HWCONFIG_BUFFER_SIZE 256
219 #define CONFIG_FSL_DEVICE_DISABLE
221 #define BOOT_TARGET_DEVICES(func) \
225 #include <config_distro_bootcmd.h>
228 #define CONFIG_EXTRA_ENV_SETTINGS \
229 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
230 "cma=64M@0x0-0xb0000000\0" \
231 "initrd_high=0xffffffff\0" \
232 "fdt_addr=0x64f00000\0" \
233 "kernel_addr=0x65000000\0" \
234 "scriptaddr=0x80000000\0" \
235 "scripthdraddr=0x80080000\0" \
236 "fdtheader_addr_r=0x80100000\0" \
237 "kernelheader_addr_r=0x80200000\0" \
238 "kernel_addr_r=0x81000000\0" \
239 "fdt_addr_r=0x90000000\0" \
240 "ramdisk_addr_r=0xa0000000\0" \
241 "load_addr=0xa0000000\0" \
242 "kernel_size=0x2800000\0" \
243 "kernel_addr_sd=0x8000\0" \
244 "kernel_size_sd=0x14000\0" \
245 "othbootargs=cma=64M@0x0-0xb0000000\0" \
247 "boot_scripts=ls1021atwr_boot.scr\0" \
248 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
249 "scan_dev_for_boot_part=" \
250 "part list ${devtype} ${devnum} devplist; " \
251 "env exists devplist || setenv devplist 1; " \
252 "for distro_bootpart in ${devplist}; do " \
253 "if fstype ${devtype} " \
254 "${devnum}:${distro_bootpart} " \
255 "bootfstype; then " \
256 "run scan_dev_for_boot; " \
259 "scan_dev_for_boot=" \
260 "echo Scanning ${devtype} " \
261 "${devnum}:${distro_bootpart}...; " \
262 "for prefix in ${boot_prefixes}; do " \
263 "run scan_dev_for_scripts; " \
267 "load ${devtype} ${devnum}:${distro_bootpart} " \
268 "${scriptaddr} ${prefix}${script}; " \
269 "env exists secureboot && load ${devtype} " \
270 "${devnum}:${distro_bootpart} " \
271 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
272 "env exists secureboot " \
273 "&& esbc_validate ${scripthdraddr};" \
274 "source ${scriptaddr}\0" \
275 "installer=load mmc 0:2 $load_addr " \
276 "/flex_installer_arm32.itb; " \
277 "bootm $load_addr#ls1021atwr\0" \
278 "qspi_bootcmd=echo Trying load from qspi..;" \
279 "sf probe && sf read $load_addr " \
280 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
281 "nor_bootcmd=echo Trying load from nor..;" \
282 "cp.b $kernel_addr $load_addr " \
283 "$kernel_size && bootm $load_addr#$board\0"
285 #define CONFIG_EXTRA_ENV_SETTINGS \
286 "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \
287 "cma=64M@0x0-0xb0000000\0" \
288 "initrd_high=0xffffffff\0" \
289 "fdt_addr=0x64f00000\0" \
290 "kernel_addr=0x61000000\0" \
291 "kernelheader_addr=0x60800000\0" \
292 "scriptaddr=0x80000000\0" \
293 "scripthdraddr=0x80080000\0" \
294 "fdtheader_addr_r=0x80100000\0" \
295 "kernelheader_addr_r=0x80200000\0" \
296 "kernel_addr_r=0x81000000\0" \
297 "kernelheader_size=0x40000\0" \
298 "fdt_addr_r=0x90000000\0" \
299 "ramdisk_addr_r=0xa0000000\0" \
300 "load_addr=0xa0000000\0" \
301 "kernel_size=0x2800000\0" \
302 "kernel_addr_sd=0x8000\0" \
303 "kernel_size_sd=0x14000\0" \
304 "kernelhdr_addr_sd=0x4000\0" \
305 "kernelhdr_size_sd=0x10\0" \
306 "othbootargs=cma=64M@0x0-0xb0000000\0" \
308 "boot_scripts=ls1021atwr_boot.scr\0" \
309 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
310 "scan_dev_for_boot_part=" \
311 "part list ${devtype} ${devnum} devplist; " \
312 "env exists devplist || setenv devplist 1; " \
313 "for distro_bootpart in ${devplist}; do " \
314 "if fstype ${devtype} " \
315 "${devnum}:${distro_bootpart} " \
316 "bootfstype; then " \
317 "run scan_dev_for_boot; " \
320 "scan_dev_for_boot=" \
321 "echo Scanning ${devtype} " \
322 "${devnum}:${distro_bootpart}...; " \
323 "for prefix in ${boot_prefixes}; do " \
324 "run scan_dev_for_scripts; " \
328 "load ${devtype} ${devnum}:${distro_bootpart} " \
329 "${scriptaddr} ${prefix}${script}; " \
330 "env exists secureboot && load ${devtype} " \
331 "${devnum}:${distro_bootpart} " \
332 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
333 "&& esbc_validate ${scripthdraddr};" \
334 "source ${scriptaddr}\0" \
335 "qspi_bootcmd=echo Trying load from qspi..;" \
336 "sf probe && sf read $load_addr " \
337 "$kernel_addr $kernel_size; env exists secureboot " \
338 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
339 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
340 "bootm $load_addr#$board\0" \
341 "nor_bootcmd=echo Trying load from nor..;" \
342 "cp.b $kernel_addr $load_addr " \
343 "$kernel_size; env exists secureboot " \
344 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
345 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
346 "bootm $load_addr#$board\0" \
347 "sd_bootcmd=echo Trying load from SD ..;" \
348 "mmcinfo && mmc read $load_addr " \
349 "$kernel_addr_sd $kernel_size_sd && " \
350 "env exists secureboot && mmc read $kernelheader_addr_r " \
351 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
352 " && esbc_validate ${kernelheader_addr_r};" \
353 "bootm $load_addr#$board\0"
357 * Miscellaneous configurable options
359 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
361 #define CONFIG_LS102XA_STREAM_ID
363 #define CONFIG_SYS_INIT_SP_OFFSET \
364 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
365 #define CONFIG_SYS_INIT_SP_ADDR \
366 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
368 #ifdef CONFIG_SPL_BUILD
369 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
371 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
378 #include <asm/fsl_secure_boot.h>
379 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */