include/configs/ls1021atwr.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019, 2021 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  12
  13 #define DDR_SDRAM_CFG                   0x470c0008
  14 #define DDR_CS0_BNDS                    0x008000bf
  15 #define DDR_CS0_CONFIG                  0x80014302
  16 #define DDR_TIMING_CFG_0                0x50550004
  17 #define DDR_TIMING_CFG_1                0xbcb38c56
  18 #define DDR_TIMING_CFG_2                0x0040d120
  19 #define DDR_TIMING_CFG_3                0x010e1000
  20 #define DDR_TIMING_CFG_4                0x00000001
  21 #define DDR_TIMING_CFG_5                0x03401400
  22 #define DDR_SDRAM_CFG_2                 0x00401010
  23 #define DDR_SDRAM_MODE                  0x00061c60
  24 #define DDR_SDRAM_MODE_2                0x00180000
  25 #define DDR_SDRAM_INTERVAL              0x18600618
  26 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  27 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  28 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  29 #define DDR_DDR_CDR1                    0x80040000
  30 #define DDR_DDR_CDR2                    0x00000001
  31 #define DDR_SDRAM_CLK_CNTL              0x02000000
  32 #define DDR_DDR_ZQ_CNTL                 0x89080600
  33 #define DDR_CS0_CONFIG_2                0
  34 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  35 #define SDRAM_CFG2_D_INIT               0x00000010
  36 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  37 #define SDRAM_CFG2_FRC_SR               0x80000000
  38 #define SDRAM_CFG_BI                    0x00000001
  39
  40 #ifdef CONFIG_SD_BOOT
  41 #ifdef CONFIG_NXP_ESBC
  42 /*
  43  * HDR would be appended at end of image and copied to DDR along
  44  * with U-Boot image.
  45  */
  46 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  47 #endif /* ifdef CONFIG_NXP_ESBC */
  48
  49 #ifdef CONFIG_U_BOOT_HDR_SIZE
  50 /*
  51  * HDR would be appended at end of image and copied to DDR along
  52  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  53  * size increases then increase this size in case of secure boot as
  54  * it uses raw u-boot image instead of fit image.
  55  */
  56 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  57 #endif
  58
  59 #define PHYS_SDRAM                      0x80000000
  60 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  61
  62 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
  63 #define CFG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
  64
  65 /*
  66  * IFC Definitions
  67  */
  68 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  69 #define CONFIG_SYS_FLASH_BASE           0x60000000
  70 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  71
  72 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  73 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  74                                 CSPR_PORT_SIZE_16 | \
  75                                 CSPR_MSEL_NOR | \
  76                                 CSPR_V)
  77 #define CFG_SYS_NOR_AMASK               IFC_AMASK(128 * 1024 * 1024)
  78
  79 /* NOR Flash Timing Params */
  80 #define CFG_SYS_NOR_CSOR                (CSOR_NOR_ADM_SHIFT(4) | \
  81                                         CSOR_NOR_TRHZ_80)
  82 #define CFG_SYS_NOR_FTIM0               (FTIM0_NOR_TACSE(0x4) | \
  83                                         FTIM0_NOR_TEADC(0x5) | \
  84                                         FTIM0_NOR_TAVDS(0x0) | \
  85                                         FTIM0_NOR_TEAHC(0x5))
  86 #define CFG_SYS_NOR_FTIM1               (FTIM1_NOR_TACO(0x35) | \
  87                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
  88                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  89 #define CFG_SYS_NOR_FTIM2               (FTIM2_NOR_TCS(0x4) | \
  90                                         FTIM2_NOR_TCH(0x4) | \
  91                                         FTIM2_NOR_TWP(0x1c) | \
  92                                         FTIM2_NOR_TWPH(0x0e))
  93 #define CFG_SYS_NOR_FTIM3               0
  94
  95 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
  96
  97 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  98
  99 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 100 #endif
 101
 102 /* CPLD */
 103
 104 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 105 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 106
 107 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 108 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 109                                         CSPR_PORT_SIZE_8 | \
 110                                         CSPR_MSEL_GPCM | \
 111                                         CSPR_V)
 112 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 113 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 114                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 115                                         CSOR_NOR_TRHZ_80)
 116
 117 /* CPLD Timing parameters for IFC GPCM */
 118 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 119                                         FTIM0_GPCM_TEADC(0xf) | \
 120                                         FTIM0_GPCM_TEAHC(0xf))
 121 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 122                                         FTIM1_GPCM_TRAD(0x3f))
 123 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 124                                         FTIM2_GPCM_TCH(0xf) | \
 125                                         FTIM2_GPCM_TWP(0xff))
 126 #define CONFIG_SYS_FPGA_FTIM3           0x0
 127 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 128 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 129 #define CONFIG_SYS_AMASK0               CFG_SYS_NOR_AMASK
 130 #define CONFIG_SYS_CSOR0                CFG_SYS_NOR_CSOR
 131 #define CONFIG_SYS_CS0_FTIM0            CFG_SYS_NOR_FTIM0
 132 #define CONFIG_SYS_CS0_FTIM1            CFG_SYS_NOR_FTIM1
 133 #define CONFIG_SYS_CS0_FTIM2            CFG_SYS_NOR_FTIM2
 134 #define CONFIG_SYS_CS0_FTIM3            CFG_SYS_NOR_FTIM3
 135 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 136 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 137 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 138 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 139 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 140 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 141 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 142 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 143
 144 /*
 145  * Serial Port
 146  */
 147 #ifndef CONFIG_LPUART
 148 #define CFG_SYS_NS16550_CLK             get_serial_clock()
 149 #endif
 150
 151 /*
 152  * I2C
 153  */
 154
 155 /* GPIO */
 156
 157 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 158 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 159
 160 #define CONFIG_HWCONFIG
 161 #define HWCONFIG_BUFFER_SIZE            256
 162
 163 #define CONFIG_FSL_DEVICE_DISABLE
 164
 165 #define BOOT_TARGET_DEVICES(func) \
 166         func(MMC, mmc, 0) \
 167         func(USB, usb, 0) \
 168         func(DHCP, dhcp, na)
 169 #include <config_distro_bootcmd.h>
 170
 171 #ifdef CONFIG_LPUART
 172 #define CONFIG_EXTRA_ENV_SETTINGS       \
 173         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 "     \
 174                 "cma=64M@0x0-0xb0000000\0" \
 175         "initrd_high=0xffffffff\0"      \
 176         "kernel_addr=0x65000000\0"      \
 177         "scriptaddr=0x80000000\0"       \
 178         "scripthdraddr=0x80080000\0"    \
 179         "fdtheader_addr_r=0x80100000\0" \
 180         "kernelheader_addr_r=0x80200000\0"      \
 181         "kernel_addr_r=0x81000000\0"    \
 182         "fdt_addr_r=0x90000000\0"       \
 183         "ramdisk_addr_r=0xa0000000\0"   \
 184         "load_addr=0xa0000000\0"        \
 185         "kernel_size=0x2800000\0"       \
 186         "kernel_addr_sd=0x8000\0"       \
 187         "kernel_size_sd=0x14000\0"      \
 188         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 189         BOOTENV                         \
 190         "boot_scripts=ls1021atwr_boot.scr\0"    \
 191         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 192                 "scan_dev_for_boot_part="       \
 193                         "part list ${devtype} ${devnum} devplist; "     \
 194                         "env exists devplist || setenv devplist 1; "    \
 195                         "for distro_bootpart in ${devplist}; do "       \
 196                         "if fstype ${devtype} "                         \
 197                                 "${devnum}:${distro_bootpart} "         \
 198                                 "bootfstype; then "                     \
 199                                 "run scan_dev_for_boot; "               \
 200                         "fi; "                  \
 201                 "done\0"                        \
 202         "scan_dev_for_boot="                              \
 203                 "echo Scanning ${devtype} "               \
 204                                 "${devnum}:${distro_bootpart}...; "  \
 205                 "for prefix in ${boot_prefixes}; do "     \
 206                         "run scan_dev_for_scripts; "      \
 207                 "done;"                                   \
 208                 "\0"                                      \
 209         "boot_a_script="                                  \
 210                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 211                         "${scriptaddr} ${prefix}${script}; "    \
 212                 "env exists secureboot && load ${devtype} "     \
 213                         "${devnum}:${distro_bootpart} "         \
 214                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 215                         "env exists secureboot "        \
 216                         "&& esbc_validate ${scripthdraddr};"    \
 217                 "source ${scriptaddr}\0"          \
 218         "installer=load mmc 0:2 $load_addr "    \
 219                 "/flex_installer_arm32.itb; "           \
 220                 "bootm $load_addr#ls1021atwr\0" \
 221         "qspi_bootcmd=echo Trying load from qspi..;"    \
 222                 "sf probe && sf read $load_addr "       \
 223                 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"        \
 224         "nor_bootcmd=echo Trying load from nor..;"      \
 225                 "cp.b $kernel_addr $load_addr "         \
 226                 "$kernel_size && bootm $load_addr#$board\0"
 227 #else
 228 #define CONFIG_EXTRA_ENV_SETTINGS       \
 229         "bootargs=root=/dev/ram0 rw console=ttyS0,115200 "      \
 230                 "cma=64M@0x0-0xb0000000\0" \
 231         "initrd_high=0xffffffff\0"      \
 232         "kernel_addr=0x61000000\0"      \
 233         "kernelheader_addr=0x60800000\0"        \
 234         "scriptaddr=0x80000000\0"       \
 235         "scripthdraddr=0x80080000\0"    \
 236         "fdtheader_addr_r=0x80100000\0" \
 237         "kernelheader_addr_r=0x80200000\0"      \
 238         "kernel_addr_r=0x81000000\0"    \
 239         "kernelheader_size=0x40000\0"   \
 240         "fdt_addr_r=0x90000000\0"       \
 241         "ramdisk_addr_r=0xa0000000\0"   \
 242         "load_addr=0xa0000000\0"        \
 243         "kernel_size=0x2800000\0"       \
 244         "kernel_addr_sd=0x8000\0"       \
 245         "kernel_size_sd=0x14000\0"      \
 246         "kernelhdr_addr_sd=0x4000\0"            \
 247         "kernelhdr_size_sd=0x10\0"              \
 248         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 249         BOOTENV                         \
 250         "boot_scripts=ls1021atwr_boot.scr\0"    \
 251         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 252                 "scan_dev_for_boot_part="       \
 253                         "part list ${devtype} ${devnum} devplist; "     \
 254                         "env exists devplist || setenv devplist 1; "    \
 255                         "for distro_bootpart in ${devplist}; do "       \
 256                         "if fstype ${devtype} "                         \
 257                                 "${devnum}:${distro_bootpart} "         \
 258                                 "bootfstype; then "                     \
 259                                 "run scan_dev_for_boot; "               \
 260                         "fi; "                  \
 261                 "done\0"                        \
 262         "scan_dev_for_boot="                              \
 263                 "echo Scanning ${devtype} "               \
 264                                 "${devnum}:${distro_bootpart}...; "  \
 265                 "for prefix in ${boot_prefixes}; do "     \
 266                         "run scan_dev_for_scripts; "      \
 267                 "done;"                                   \
 268                 "\0"                                      \
 269         "boot_a_script="                                  \
 270                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 271                         "${scriptaddr} ${prefix}${script}; "    \
 272                 "env exists secureboot && load ${devtype} "     \
 273                         "${devnum}:${distro_bootpart} "         \
 274                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 275                         "&& esbc_validate ${scripthdraddr};"    \
 276                 "source ${scriptaddr}\0"          \
 277         "qspi_bootcmd=echo Trying load from qspi..;"    \
 278                 "sf probe && sf read $load_addr "       \
 279                 "$kernel_addr $kernel_size; env exists secureboot "     \
 280                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 281                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 282                 "bootm $load_addr#$board\0" \
 283         "nor_bootcmd=echo Trying load from nor..;"      \
 284                 "cp.b $kernel_addr $load_addr "         \
 285                 "$kernel_size; env exists secureboot "  \
 286                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
 287                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 288                 "bootm $load_addr#$board\0"     \
 289         "sd_bootcmd=echo Trying load from SD ..;"       \
 290                 "mmcinfo && mmc read $load_addr "       \
 291                 "$kernel_addr_sd $kernel_size_sd && "   \
 292                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
 293                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 294                 " && esbc_validate ${kernelheader_addr_r};"     \
 295                 "bootm $load_addr#$board\0"
 296 #endif
 297
 298 /*
 299  * Miscellaneous configurable options
 300  */
 301 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 302
 303 #define CONFIG_LS102XA_STREAM_ID
 304
 305 /*
 306  * Environment
 307  */
 308
 309 #include <asm/fsl_secure_boot.h>
 310
 311 #endif