include/configs/ls1021atwr.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019, 2021 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  12
  13 #define DDR_SDRAM_CFG                   0x470c0008
  14 #define DDR_CS0_BNDS                    0x008000bf
  15 #define DDR_CS0_CONFIG                  0x80014302
  16 #define DDR_TIMING_CFG_0                0x50550004
  17 #define DDR_TIMING_CFG_1                0xbcb38c56
  18 #define DDR_TIMING_CFG_2                0x0040d120
  19 #define DDR_TIMING_CFG_3                0x010e1000
  20 #define DDR_TIMING_CFG_4                0x00000001
  21 #define DDR_TIMING_CFG_5                0x03401400
  22 #define DDR_SDRAM_CFG_2                 0x00401010
  23 #define DDR_SDRAM_MODE                  0x00061c60
  24 #define DDR_SDRAM_MODE_2                0x00180000
  25 #define DDR_SDRAM_INTERVAL              0x18600618
  26 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  27 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  28 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  29 #define DDR_DDR_CDR1                    0x80040000
  30 #define DDR_DDR_CDR2                    0x00000001
  31 #define DDR_SDRAM_CLK_CNTL              0x02000000
  32 #define DDR_DDR_ZQ_CNTL                 0x89080600
  33 #define DDR_CS0_CONFIG_2                0
  34 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  35 #define SDRAM_CFG2_D_INIT               0x00000010
  36 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  37 #define SDRAM_CFG2_FRC_SR               0x80000000
  38 #define SDRAM_CFG_BI                    0x00000001
  39
  40 #ifdef CONFIG_SD_BOOT
  41 #ifdef CONFIG_NXP_ESBC
  42 /*
  43  * HDR would be appended at end of image and copied to DDR along
  44  * with U-Boot image.
  45  */
  46 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  47 #endif /* ifdef CONFIG_NXP_ESBC */
  48
  49 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  50                 CONFIG_SYS_MONITOR_LEN)
  51 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  52
  53 #ifdef CONFIG_U_BOOT_HDR_SIZE
  54 /*
  55  * HDR would be appended at end of image and copied to DDR along
  56  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  57  * size increases then increase this size in case of secure boot as
  58  * it uses raw u-boot image instead of fit image.
  59  */
  60 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  61 #else
  62 #define CONFIG_SYS_MONITOR_LEN          0x100000
  63 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  64 #endif
  65
  66 #define PHYS_SDRAM                      0x80000000
  67 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  68
  69 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
  70 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
  71
  72 /*
  73  * IFC Definitions
  74  */
  75 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  76 #define CONFIG_SYS_FLASH_BASE           0x60000000
  77 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  78
  79 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  80 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  81                                 CSPR_PORT_SIZE_16 | \
  82                                 CSPR_MSEL_NOR | \
  83                                 CSPR_V)
  84 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  85
  86 /* NOR Flash Timing Params */
  87 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  88                                         CSOR_NOR_TRHZ_80)
  89 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  90                                         FTIM0_NOR_TEADC(0x5) | \
  91                                         FTIM0_NOR_TAVDS(0x0) | \
  92                                         FTIM0_NOR_TEAHC(0x5))
  93 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  94                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
  95                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  96 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  97                                         FTIM2_NOR_TCH(0x4) | \
  98                                         FTIM2_NOR_TWP(0x1c) | \
  99                                         FTIM2_NOR_TWPH(0x0e))
 100 #define CONFIG_SYS_NOR_FTIM3            0
 101
 102 #define CONFIG_SYS_FLASH_QUIET_TEST
 103 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 104
 105 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 106 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 107 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 108
 109 #define CONFIG_SYS_FLASH_EMPTY_INFO
 110 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 111
 112 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 113 #endif
 114
 115 /* CPLD */
 116
 117 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 118 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 119
 120 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 121 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 122                                         CSPR_PORT_SIZE_8 | \
 123                                         CSPR_MSEL_GPCM | \
 124                                         CSPR_V)
 125 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 126 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 127                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 128                                         CSOR_NOR_TRHZ_80)
 129
 130 /* CPLD Timing parameters for IFC GPCM */
 131 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 132                                         FTIM0_GPCM_TEADC(0xf) | \
 133                                         FTIM0_GPCM_TEAHC(0xf))
 134 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 135                                         FTIM1_GPCM_TRAD(0x3f))
 136 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 137                                         FTIM2_GPCM_TCH(0xf) | \
 138                                         FTIM2_GPCM_TWP(0xff))
 139 #define CONFIG_SYS_FPGA_FTIM3           0x0
 140 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 141 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 142 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 143 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 144 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 145 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 146 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 147 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 148 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 149 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 150 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 151 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 152 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 153 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 154 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 155 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 156
 157 /*
 158  * Serial Port
 159  */
 160 #ifndef CONFIG_LPUART
 161 #define CONFIG_SYS_NS16550_SERIAL
 162 #ifndef CONFIG_DM_SERIAL
 163 #define CONFIG_SYS_NS16550_REG_SIZE     1
 164 #endif
 165 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 166 #endif
 167
 168 /*
 169  * I2C
 170  */
 171
 172 /* GPIO */
 173
 174 /* EEPROM */
 175 #define CONFIG_SYS_I2C_EEPROM_NXID
 176 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 177
 178 /* PCIe */
 179 #define CONFIG_PCIE1            /* PCIE controller 1 */
 180 #define CONFIG_PCIE2            /* PCIE controller 2 */
 181
 182 #ifdef CONFIG_PCI
 183 #define CONFIG_PCI_SCAN_SHOW
 184 #endif
 185
 186 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 187 #define CONFIG_LAYERSCAPE_NS_ACCESS
 188 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 189
 190 #define CONFIG_HWCONFIG
 191 #define HWCONFIG_BUFFER_SIZE            256
 192
 193 #define CONFIG_FSL_DEVICE_DISABLE
 194
 195 #define BOOT_TARGET_DEVICES(func) \
 196         func(MMC, mmc, 0) \
 197         func(USB, usb, 0) \
 198         func(DHCP, dhcp, na)
 199 #include <config_distro_bootcmd.h>
 200
 201 #ifdef CONFIG_LPUART
 202 #define CONFIG_EXTRA_ENV_SETTINGS       \
 203         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 "     \
 204                 "cma=64M@0x0-0xb0000000\0" \
 205         "initrd_high=0xffffffff\0"      \
 206         "kernel_addr=0x65000000\0"      \
 207         "scriptaddr=0x80000000\0"       \
 208         "scripthdraddr=0x80080000\0"    \
 209         "fdtheader_addr_r=0x80100000\0" \
 210         "kernelheader_addr_r=0x80200000\0"      \
 211         "kernel_addr_r=0x81000000\0"    \
 212         "fdt_addr_r=0x90000000\0"       \
 213         "ramdisk_addr_r=0xa0000000\0"   \
 214         "load_addr=0xa0000000\0"        \
 215         "kernel_size=0x2800000\0"       \
 216         "kernel_addr_sd=0x8000\0"       \
 217         "kernel_size_sd=0x14000\0"      \
 218         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 219         BOOTENV                         \
 220         "boot_scripts=ls1021atwr_boot.scr\0"    \
 221         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 222                 "scan_dev_for_boot_part="       \
 223                         "part list ${devtype} ${devnum} devplist; "     \
 224                         "env exists devplist || setenv devplist 1; "    \
 225                         "for distro_bootpart in ${devplist}; do "       \
 226                         "if fstype ${devtype} "                         \
 227                                 "${devnum}:${distro_bootpart} "         \
 228                                 "bootfstype; then "                     \
 229                                 "run scan_dev_for_boot; "               \
 230                         "fi; "                  \
 231                 "done\0"                        \
 232         "scan_dev_for_boot="                              \
 233                 "echo Scanning ${devtype} "               \
 234                                 "${devnum}:${distro_bootpart}...; "  \
 235                 "for prefix in ${boot_prefixes}; do "     \
 236                         "run scan_dev_for_scripts; "      \
 237                 "done;"                                   \
 238                 "\0"                                      \
 239         "boot_a_script="                                  \
 240                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 241                         "${scriptaddr} ${prefix}${script}; "    \
 242                 "env exists secureboot && load ${devtype} "     \
 243                         "${devnum}:${distro_bootpart} "         \
 244                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 245                         "env exists secureboot "        \
 246                         "&& esbc_validate ${scripthdraddr};"    \
 247                 "source ${scriptaddr}\0"          \
 248         "installer=load mmc 0:2 $load_addr "    \
 249                 "/flex_installer_arm32.itb; "           \
 250                 "bootm $load_addr#ls1021atwr\0" \
 251         "qspi_bootcmd=echo Trying load from qspi..;"    \
 252                 "sf probe && sf read $load_addr "       \
 253                 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"        \
 254         "nor_bootcmd=echo Trying load from nor..;"      \
 255                 "cp.b $kernel_addr $load_addr "         \
 256                 "$kernel_size && bootm $load_addr#$board\0"
 257 #else
 258 #define CONFIG_EXTRA_ENV_SETTINGS       \
 259         "bootargs=root=/dev/ram0 rw console=ttyS0,115200 "      \
 260                 "cma=64M@0x0-0xb0000000\0" \
 261         "initrd_high=0xffffffff\0"      \
 262         "kernel_addr=0x61000000\0"      \
 263         "kernelheader_addr=0x60800000\0"        \
 264         "scriptaddr=0x80000000\0"       \
 265         "scripthdraddr=0x80080000\0"    \
 266         "fdtheader_addr_r=0x80100000\0" \
 267         "kernelheader_addr_r=0x80200000\0"      \
 268         "kernel_addr_r=0x81000000\0"    \
 269         "kernelheader_size=0x40000\0"   \
 270         "fdt_addr_r=0x90000000\0"       \
 271         "ramdisk_addr_r=0xa0000000\0"   \
 272         "load_addr=0xa0000000\0"        \
 273         "kernel_size=0x2800000\0"       \
 274         "kernel_addr_sd=0x8000\0"       \
 275         "kernel_size_sd=0x14000\0"      \
 276         "kernelhdr_addr_sd=0x4000\0"            \
 277         "kernelhdr_size_sd=0x10\0"              \
 278         "othbootargs=cma=64M@0x0-0xb0000000\0"  \
 279         BOOTENV                         \
 280         "boot_scripts=ls1021atwr_boot.scr\0"    \
 281         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 282                 "scan_dev_for_boot_part="       \
 283                         "part list ${devtype} ${devnum} devplist; "     \
 284                         "env exists devplist || setenv devplist 1; "    \
 285                         "for distro_bootpart in ${devplist}; do "       \
 286                         "if fstype ${devtype} "                         \
 287                                 "${devnum}:${distro_bootpart} "         \
 288                                 "bootfstype; then "                     \
 289                                 "run scan_dev_for_boot; "               \
 290                         "fi; "                  \
 291                 "done\0"                        \
 292         "scan_dev_for_boot="                              \
 293                 "echo Scanning ${devtype} "               \
 294                                 "${devnum}:${distro_bootpart}...; "  \
 295                 "for prefix in ${boot_prefixes}; do "     \
 296                         "run scan_dev_for_scripts; "      \
 297                 "done;"                                   \
 298                 "\0"                                      \
 299         "boot_a_script="                                  \
 300                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 301                         "${scriptaddr} ${prefix}${script}; "    \
 302                 "env exists secureboot && load ${devtype} "     \
 303                         "${devnum}:${distro_bootpart} "         \
 304                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 305                         "&& esbc_validate ${scripthdraddr};"    \
 306                 "source ${scriptaddr}\0"          \
 307         "qspi_bootcmd=echo Trying load from qspi..;"    \
 308                 "sf probe && sf read $load_addr "       \
 309                 "$kernel_addr $kernel_size; env exists secureboot "     \
 310                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 311                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 312                 "bootm $load_addr#$board\0" \
 313         "nor_bootcmd=echo Trying load from nor..;"      \
 314                 "cp.b $kernel_addr $load_addr "         \
 315                 "$kernel_size; env exists secureboot "  \
 316                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
 317                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 318                 "bootm $load_addr#$board\0"     \
 319         "sd_bootcmd=echo Trying load from SD ..;"       \
 320                 "mmcinfo && mmc read $load_addr "       \
 321                 "$kernel_addr_sd $kernel_size_sd && "   \
 322                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
 323                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 324                 " && esbc_validate ${kernelheader_addr_r};"     \
 325                 "bootm $load_addr#$board\0"
 326 #endif
 327
 328 /*
 329  * Miscellaneous configurable options
 330  */
 331 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 332
 333 #define CONFIG_LS102XA_STREAM_ID
 334
 335 /*
 336  * Environment
 337  */
 338
 339 #include <asm/fsl_secure_boot.h>
 340 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 341
 342 #endif