2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_LS102XA
12 #define CONFIG_ARMV7_PSCI_1_0
14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
16 #define CONFIG_SYS_FSL_CLK
18 #define CONFIG_SKIP_LOWLEVEL_INIT
19 #define CONFIG_BOARD_EARLY_INIT_F
20 #define CONFIG_DEEP_SLEEP
21 #ifdef CONFIG_DEEP_SLEEP
22 #define CONFIG_SILENT_CONSOLE
26 * Size of malloc() pool
28 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
30 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
31 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
38 * EHCI Support - disbaled by default as
39 * there is no signal coming out of soc on
40 * this board for this controller. However,
41 * the silicon still has this controller,
42 * and anyone can use this controller by
43 * taking signals out on their board.
46 /*#define CONFIG_HAS_FSL_DR_USB*/
48 #ifdef CONFIG_HAS_FSL_DR_USB
49 #define CONFIG_USB_EHCI
50 #define CONFIG_USB_EHCI_FSL
51 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
54 /* XHCI Support - enabled by default */
55 #define CONFIG_HAS_FSL_XHCI_USB
57 #ifdef CONFIG_HAS_FSL_XHCI_USB
58 #define CONFIG_USB_XHCI_FSL
59 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
60 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
64 * Generic Timer Definitions
66 #define GENERIC_TIMER_CLK 12500000
68 #define CONFIG_SYS_CLK_FREQ 100000000
69 #define CONFIG_DDR_CLK_FREQ 100000000
71 #define DDR_SDRAM_CFG 0x470c0008
72 #define DDR_CS0_BNDS 0x008000bf
73 #define DDR_CS0_CONFIG 0x80014302
74 #define DDR_TIMING_CFG_0 0x50550004
75 #define DDR_TIMING_CFG_1 0xbcb38c56
76 #define DDR_TIMING_CFG_2 0x0040d120
77 #define DDR_TIMING_CFG_3 0x010e1000
78 #define DDR_TIMING_CFG_4 0x00000001
79 #define DDR_TIMING_CFG_5 0x03401400
80 #define DDR_SDRAM_CFG_2 0x00401010
81 #define DDR_SDRAM_MODE 0x00061c60
82 #define DDR_SDRAM_MODE_2 0x00180000
83 #define DDR_SDRAM_INTERVAL 0x18600618
84 #define DDR_DDR_WRLVL_CNTL 0x8655f605
85 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
86 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
87 #define DDR_DDR_CDR1 0x80040000
88 #define DDR_DDR_CDR2 0x00000001
89 #define DDR_SDRAM_CLK_CNTL 0x02000000
90 #define DDR_DDR_ZQ_CNTL 0x89080600
91 #define DDR_CS0_CONFIG_2 0
92 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
93 #define SDRAM_CFG2_D_INIT 0x00000010
94 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
95 #define SDRAM_CFG2_FRC_SR 0x80000000
96 #define SDRAM_CFG_BI 0x00000001
98 #ifdef CONFIG_RAMBOOT_PBL
99 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
102 #ifdef CONFIG_SD_BOOT
103 #ifdef CONFIG_SD_BOOT_QSPI
104 #define CONFIG_SYS_FSL_PBL_RCW \
105 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
107 #define CONFIG_SYS_FSL_PBL_RCW \
108 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
110 #define CONFIG_SPL_FRAMEWORK
111 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
112 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
114 #ifdef CONFIG_SECURE_BOOT
115 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
117 * HDR would be appended at end of image and copied to DDR along
120 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \
121 (CONFIG_U_BOOT_HDR_SIZE / 512)
123 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
124 #endif /* ifdef CONFIG_SECURE_BOOT */
126 #define CONFIG_SPL_TEXT_BASE 0x10000000
127 #define CONFIG_SPL_MAX_SIZE 0x1a000
128 #define CONFIG_SPL_STACK 0x1001d000
129 #define CONFIG_SPL_PAD_TO 0x1c000
130 #define CONFIG_SYS_TEXT_BASE 0x82000000
132 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
133 CONFIG_SYS_MONITOR_LEN)
134 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
135 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
136 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
138 #ifdef CONFIG_U_BOOT_HDR_SIZE
140 * HDR would be appended at end of image and copied to DDR along
141 * with U-Boot image. Here u-boot max. size is 512K. So if binary
142 * size increases then increase this size in case of secure boot as
143 * it uses raw u-boot image instead of fit image.
145 #define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE)
147 #define CONFIG_SYS_MONITOR_LEN 0x80000
148 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
151 #ifdef CONFIG_QSPI_BOOT
152 #define CONFIG_SYS_TEXT_BASE 0x40010000
155 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
156 #define CONFIG_SYS_NO_FLASH
159 #ifndef CONFIG_SYS_TEXT_BASE
160 #define CONFIG_SYS_TEXT_BASE 0x60100000
163 #define CONFIG_NR_DRAM_BANKS 1
164 #define PHYS_SDRAM 0x80000000
165 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
167 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
168 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
170 #define CONFIG_SYS_HAS_SERDES
172 #define CONFIG_FSL_CAAM /* Enable CAAM */
174 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
175 !defined(CONFIG_QSPI_BOOT)
182 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
183 #define CONFIG_FSL_IFC
184 #define CONFIG_SYS_FLASH_BASE 0x60000000
185 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
187 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
188 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
189 CSPR_PORT_SIZE_16 | \
192 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
194 /* NOR Flash Timing Params */
195 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
197 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
198 FTIM0_NOR_TEADC(0x5) | \
199 FTIM0_NOR_TAVDS(0x0) | \
200 FTIM0_NOR_TEAHC(0x5))
201 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
202 FTIM1_NOR_TRAD_NOR(0x1A) | \
203 FTIM1_NOR_TSEQRAD_NOR(0x13))
204 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
205 FTIM2_NOR_TCH(0x4) | \
206 FTIM2_NOR_TWP(0x1c) | \
207 FTIM2_NOR_TWPH(0x0e))
208 #define CONFIG_SYS_NOR_FTIM3 0
210 #define CONFIG_FLASH_CFI_DRIVER
211 #define CONFIG_SYS_FLASH_CFI
212 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
213 #define CONFIG_SYS_FLASH_QUIET_TEST
214 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
216 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
217 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
218 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
219 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
221 #define CONFIG_SYS_FLASH_EMPTY_INFO
222 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
224 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
225 #define CONFIG_SYS_WRITE_SWAPPED_DATA
230 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
231 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
233 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
234 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
238 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
239 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
240 CSOR_NOR_NOR_MODE_AVD_NOR | \
243 /* CPLD Timing parameters for IFC GPCM */
244 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
245 FTIM0_GPCM_TEADC(0xf) | \
246 FTIM0_GPCM_TEAHC(0xf))
247 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
248 FTIM1_GPCM_TRAD(0x3f))
249 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
250 FTIM2_GPCM_TCH(0xf) | \
251 FTIM2_GPCM_TWP(0xff))
252 #define CONFIG_SYS_FPGA_FTIM3 0x0
253 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
254 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
255 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
256 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
257 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
258 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
259 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
260 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
261 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
262 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
263 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
264 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
265 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
266 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
267 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
268 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
274 #define CONFIG_LPUART_32B_REG
276 #define CONFIG_CONS_INDEX 1
277 #define CONFIG_SYS_NS16550_SERIAL
278 #ifndef CONFIG_DM_SERIAL
279 #define CONFIG_SYS_NS16550_REG_SIZE 1
281 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
284 #define CONFIG_BAUDRATE 115200
289 #define CONFIG_SYS_I2C
290 #define CONFIG_SYS_I2C_MXC
291 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
292 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
293 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
296 #define CONFIG_ID_EEPROM
297 #define CONFIG_SYS_I2C_EEPROM_NXID
298 #define CONFIG_SYS_EEPROM_BUS_NUM 1
299 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
300 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
301 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
302 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
308 #define CONFIG_FSL_ESDHC
309 #define CONFIG_GENERIC_MMC
311 #define CONFIG_DOS_PARTITION
314 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
316 #define QSPI0_AMBA_BASE 0x40000000
317 #define FSL_QSPI_FLASH_SIZE (1 << 24)
318 #define FSL_QSPI_FLASH_NUM 2
324 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
325 #define CONFIG_DM_SPI_FLASH
331 #define CONFIG_FSL_DCU_FB
333 #ifdef CONFIG_FSL_DCU_FB
335 #define CONFIG_CMD_BMP
336 #define CONFIG_CFB_CONSOLE
337 #define CONFIG_VGA_AS_SINGLE_DEVICE
338 #define CONFIG_VIDEO_LOGO
339 #define CONFIG_VIDEO_BMP_LOGO
340 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
342 #define CONFIG_FSL_DCU_SII9022A
343 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
344 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
350 #define CONFIG_TSEC_ENET
352 #ifdef CONFIG_TSEC_ENET
354 #define CONFIG_MII_DEFAULT_TSEC 1
355 #define CONFIG_TSEC1 1
356 #define CONFIG_TSEC1_NAME "eTSEC1"
357 #define CONFIG_TSEC2 1
358 #define CONFIG_TSEC2_NAME "eTSEC2"
359 #define CONFIG_TSEC3 1
360 #define CONFIG_TSEC3_NAME "eTSEC3"
362 #define TSEC1_PHY_ADDR 2
363 #define TSEC2_PHY_ADDR 0
364 #define TSEC3_PHY_ADDR 1
366 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
367 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
368 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
370 #define TSEC1_PHYIDX 0
371 #define TSEC2_PHYIDX 0
372 #define TSEC3_PHYIDX 0
374 #define CONFIG_ETHPRIME "eTSEC1"
376 #define CONFIG_PHY_GIGE
377 #define CONFIG_PHYLIB
378 #define CONFIG_PHY_ATHEROS
380 #define CONFIG_HAS_ETH0
381 #define CONFIG_HAS_ETH1
382 #define CONFIG_HAS_ETH2
386 #define CONFIG_PCI /* Enable PCI/PCIE */
387 #define CONFIG_PCIE1 /* PCIE controller 1 */
388 #define CONFIG_PCIE2 /* PCIE controller 2 */
389 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
390 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
392 #define CONFIG_SYS_PCI_64BIT
394 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
395 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
396 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
397 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
399 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
400 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
401 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
403 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
404 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
405 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
408 #define CONFIG_PCI_PNP
409 #define CONFIG_PCI_SCAN_SHOW
410 #define CONFIG_CMD_PCI
413 #define CONFIG_CMDLINE_TAG
414 #define CONFIG_CMDLINE_EDITING
416 #define CONFIG_ARMV7_NONSEC
417 #define CONFIG_ARMV7_VIRT
418 #define CONFIG_PEN_ADDR_BIG_ENDIAN
419 #define CONFIG_LAYERSCAPE_NS_ACCESS
420 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
421 #define CONFIG_TIMER_CLK_FREQ 12500000
423 #define CONFIG_HWCONFIG
424 #define HWCONFIG_BUFFER_SIZE 256
426 #define CONFIG_FSL_DEVICE_DISABLE
430 #define CONFIG_EXTRA_ENV_SETTINGS \
431 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
432 "initrd_high=0xffffffff\0" \
433 "fdt_high=0xffffffff\0"
435 #define CONFIG_EXTRA_ENV_SETTINGS \
436 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
437 "initrd_high=0xffffffff\0" \
438 "fdt_high=0xffffffff\0"
442 * Miscellaneous configurable options
444 #define CONFIG_SYS_LONGHELP /* undef to save memory */
445 #define CONFIG_AUTO_COMPLETE
446 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
447 #define CONFIG_SYS_PBSIZE \
448 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
449 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
450 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
452 #define CONFIG_SYS_MEMTEST_START 0x80000000
453 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
455 #define CONFIG_SYS_LOAD_ADDR 0x82000000
457 #define CONFIG_LS102XA_STREAM_ID
461 * The stack sizes are set up in start.S using the settings below
463 #define CONFIG_STACKSIZE (30 * 1024)
465 #define CONFIG_SYS_INIT_SP_OFFSET \
466 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
467 #define CONFIG_SYS_INIT_SP_ADDR \
468 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
470 #ifdef CONFIG_SPL_BUILD
471 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
473 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
476 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000
481 #define CONFIG_ENV_OVERWRITE
483 #if defined(CONFIG_SD_BOOT)
484 #define CONFIG_ENV_OFFSET 0x100000
485 #define CONFIG_ENV_IS_IN_MMC
486 #define CONFIG_SYS_MMC_ENV_DEV 0
487 #define CONFIG_ENV_SIZE 0x20000
488 #elif defined(CONFIG_QSPI_BOOT)
489 #define CONFIG_ENV_IS_IN_SPI_FLASH
490 #define CONFIG_ENV_SIZE 0x2000
491 #define CONFIG_ENV_OFFSET 0x100000
492 #define CONFIG_ENV_SECT_SIZE 0x10000
494 #define CONFIG_ENV_IS_IN_FLASH
495 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
496 #define CONFIG_ENV_SIZE 0x20000
497 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
500 #define CONFIG_MISC_INIT_R
502 /* Hash command with SHA acceleration supported in hardware */
503 #ifdef CONFIG_FSL_CAAM
504 #define CONFIG_CMD_HASH
505 #define CONFIG_SHA_HW_ACCEL
508 #include <asm/fsl_secure_boot.h>
509 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */