include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_DEEP_SLEEP
  13
  14 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  15 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  16
  17 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  18 #define CONFIG_QIXIS_I2C_ACCESS
  19 #endif
  20
  21 #ifdef CONFIG_SD_BOOT
  22 #define CONFIG_SPL_MAX_SIZE             0x1a000
  23 #define CONFIG_SPL_STACK                0x1001d000
  24 #define CONFIG_SPL_PAD_TO               0x1c000
  25
  26 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  27                 CONFIG_SYS_MONITOR_LEN)
  28 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  29 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  30 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  31 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  32 #endif
  33
  34 #ifdef CONFIG_NAND_BOOT
  35 #define CONFIG_SPL_MAX_SIZE             0x1a000
  36 #define CONFIG_SPL_STACK                0x1001d000
  37 #define CONFIG_SPL_PAD_TO               0x1c000
  38
  39 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  40 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  41 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  42
  43 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  44 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  45 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  46 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  47 #define CONFIG_SYS_MONITOR_LEN          0x80000
  48 #endif
  49
  50 #define SPD_EEPROM_ADDRESS              0x51
  51 #define CONFIG_SYS_SPD_BUS_NUM          0
  52
  53 #ifndef CONFIG_SYS_FSL_DDR4
  54 #define CONFIG_SYS_DDR_RAW_TIMING
  55 #endif
  56 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  57
  58 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  59 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  60
  61 #ifdef CONFIG_DDR_ECC
  62 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  63 #endif
  64
  65 /*
  66  * IFC Definitions
  67  */
  68 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  69 #define CONFIG_SYS_FLASH_BASE           0x60000000
  70 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  71
  72 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  73 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  74                                 CSPR_PORT_SIZE_16 | \
  75                                 CSPR_MSEL_NOR | \
  76                                 CSPR_V)
  77 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  78 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  79                                 + 0x8000000) | \
  80                                 CSPR_PORT_SIZE_16 | \
  81                                 CSPR_MSEL_NOR | \
  82                                 CSPR_V)
  83 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  84
  85 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  86                                         CSOR_NOR_TRHZ_80)
  87 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  88                                         FTIM0_NOR_TEADC(0x5) | \
  89                                         FTIM0_NOR_TEAHC(0x5))
  90 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  91                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  92                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  93 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  94                                         FTIM2_NOR_TCH(0x4) | \
  95                                         FTIM2_NOR_TWPH(0xe) | \
  96                                         FTIM2_NOR_TWP(0x1c))
  97 #define CONFIG_SYS_NOR_FTIM3            0
  98
  99 #define CONFIG_SYS_FLASH_QUIET_TEST
 100 #define CONFIG_FLASH_SHOW_PROGRESS      45
 101 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 102
 103 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 104 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 105 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 106
 107 #define CONFIG_SYS_FLASH_EMPTY_INFO
 108 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 109                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 110
 111 /*
 112  * NAND Flash Definitions
 113  */
 114
 115 #define CONFIG_SYS_NAND_BASE            0x7e800000
 116 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 117
 118 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 119
 120 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 121                                 | CSPR_PORT_SIZE_8      \
 122                                 | CSPR_MSEL_NAND        \
 123                                 | CSPR_V)
 124 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 125 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 126                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 127                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 128                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 129                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 130                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 131                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 132
 133 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 134                                         FTIM0_NAND_TWP(0x18)   | \
 135                                         FTIM0_NAND_TWCHT(0x7) | \
 136                                         FTIM0_NAND_TWH(0xa))
 137 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 138                                         FTIM1_NAND_TWBE(0x39)  | \
 139                                         FTIM1_NAND_TRR(0xe)   | \
 140                                         FTIM1_NAND_TRP(0x18))
 141 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 142                                         FTIM2_NAND_TREH(0xa) | \
 143                                         FTIM2_NAND_TWHRE(0x1e))
 144 #define CONFIG_SYS_NAND_FTIM3           0x0
 145
 146 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 147 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 148 #endif
 149
 150 /*
 151  * QIXIS Definitions
 152  */
 153 #define CONFIG_FSL_QIXIS
 154
 155 #ifdef CONFIG_FSL_QIXIS
 156 #define QIXIS_BASE                      0x7fb00000
 157 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 158 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 159 #define QIXIS_LBMAP_SWITCH              6
 160 #define QIXIS_LBMAP_MASK                0x0f
 161 #define QIXIS_LBMAP_SHIFT               0
 162 #define QIXIS_LBMAP_DFLTBANK            0x00
 163 #define QIXIS_LBMAP_ALTBANK             0x04
 164 #define QIXIS_PWR_CTL                   0x21
 165 #define QIXIS_PWR_CTL_POWEROFF          0x80
 166 #define QIXIS_RST_CTL_RESET             0x44
 167 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 168 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 169 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 170 #define QIXIS_CTL_SYS                   0x5
 171 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 172 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 173 #define QIXIS_RST_FORCE_3               0x45
 174 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 175 #define QIXIS_PWR_CTL2                  0x21
 176 #define QIXIS_PWR_CTL2_PCTL             0x2
 177
 178 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 179 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 180                                         CSPR_PORT_SIZE_8 | \
 181                                         CSPR_MSEL_GPCM | \
 182                                         CSPR_V)
 183 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 184 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 185                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 186                                         CSOR_NOR_TRHZ_80)
 187
 188 /*
 189  * QIXIS Timing parameters for IFC GPCM
 190  */
 191 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 192                                         FTIM0_GPCM_TEADC(0xe) | \
 193                                         FTIM0_GPCM_TEAHC(0xe))
 194 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 195                                         FTIM1_GPCM_TRAD(0x1f))
 196 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 197                                         FTIM2_GPCM_TCH(0xe) | \
 198                                         FTIM2_GPCM_TWP(0xf0))
 199 #define CONFIG_SYS_FPGA_FTIM3           0x0
 200 #endif
 201
 202 #if defined(CONFIG_NAND_BOOT)
 203 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 204 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 205 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 206 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 207 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 208 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 209 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 210 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 211 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 212 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 213 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 214 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 215 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 216 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 217 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 218 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 219 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 220 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 221 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 222 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 223 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 224 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 225 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 226 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 227 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 228 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 229 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 230 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 231 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 232 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 233 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 234 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 235 #else
 236 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 237 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 238 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 239 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 240 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 241 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 242 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 243 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 244 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 245 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 246 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 247 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 248 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 249 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 250 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 251 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 252 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 253 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 254 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 255 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 256 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 257 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 258 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 259 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 260 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 261 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 262 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 263 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 264 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 265 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 266 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 267 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 268 #endif
 269
 270 /*
 271  * Serial Port
 272  */
 273 #ifdef CONFIG_LPUART
 274 #define CONFIG_LPUART_32B_REG
 275 #else
 276 #define CONFIG_SYS_NS16550_SERIAL
 277 #ifndef CONFIG_DM_SERIAL
 278 #define CONFIG_SYS_NS16550_REG_SIZE     1
 279 #endif
 280 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 281 #endif
 282
 283 /*
 284  * I2C
 285  */
 286
 287 /* GPIO */
 288
 289 /* EEPROM */
 290 #define CONFIG_SYS_I2C_EEPROM_NXID
 291 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 292
 293 /*
 294  * I2C bus multiplexer
 295  */
 296 #define I2C_MUX_PCA_ADDR_PRI            0x77
 297 #define I2C_MUX_CH_DEFAULT              0x8
 298 #define I2C_MUX_CH_CH7301               0xC
 299
 300 /*
 301  * MMC
 302  */
 303
 304 /*
 305  * Video
 306  */
 307 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 308 #define CONFIG_VIDEO_BMP_LOGO
 309
 310 #define CONFIG_FSL_DIU_CH7301
 311 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 312 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
 313 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 314 #endif
 315
 316 /*
 317  * eTSEC
 318  */
 319
 320 #ifdef CONFIG_TSEC_ENET
 321 #define CONFIG_MII_DEFAULT_TSEC         3
 322 #define CONFIG_TSEC1                    1
 323 #define CONFIG_TSEC1_NAME               "eTSEC1"
 324 #define CONFIG_TSEC2                    1
 325 #define CONFIG_TSEC2_NAME               "eTSEC2"
 326 #define CONFIG_TSEC3                    1
 327 #define CONFIG_TSEC3_NAME               "eTSEC3"
 328
 329 #define TSEC1_PHY_ADDR                  1
 330 #define TSEC2_PHY_ADDR                  2
 331 #define TSEC3_PHY_ADDR                  3
 332
 333 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 334 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 335 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 336
 337 #define TSEC1_PHYIDX                    0
 338 #define TSEC2_PHYIDX                    0
 339 #define TSEC3_PHYIDX                    0
 340
 341 #define CONFIG_ETHPRIME                 "eTSEC1"
 342
 343 #define CONFIG_HAS_ETH0
 344 #define CONFIG_HAS_ETH1
 345 #define CONFIG_HAS_ETH2
 346
 347 #define CONFIG_FSL_SGMII_RISER          1
 348 #define SGMII_RISER_PHY_OFFSET          0x1b
 349
 350 #ifdef CONFIG_FSL_SGMII_RISER
 351 #define CONFIG_SYS_TBIPA_VALUE          8
 352 #endif
 353
 354 #endif
 355
 356 /* PCIe */
 357 #define CONFIG_PCIE1            /* PCIE controller 1 */
 358 #define CONFIG_PCIE2            /* PCIE controller 2 */
 359
 360 #ifdef CONFIG_PCI
 361 #define CONFIG_PCI_SCAN_SHOW
 362 #endif
 363
 364 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 365 #define CONFIG_LAYERSCAPE_NS_ACCESS
 366 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 367 #define COUNTER_FREQUENCY               12500000
 368
 369 #define CONFIG_HWCONFIG
 370 #define HWCONFIG_BUFFER_SIZE            256
 371
 372 #define CONFIG_FSL_DEVICE_DISABLE
 373
 374 #ifdef CONFIG_LPUART
 375 #define CONFIG_EXTRA_ENV_SETTINGS       \
 376         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 377         "initrd_high=0xffffffff\0"      \
 378         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 379 #else
 380 #define CONFIG_EXTRA_ENV_SETTINGS       \
 381         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 382         "initrd_high=0xffffffff\0"      \
 383         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 384 #endif
 385
 386 /*
 387  * Miscellaneous configurable options
 388  */
 389 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 390
 391 #define CONFIG_LS102XA_STREAM_ID
 392
 393 #define CONFIG_SYS_INIT_SP_OFFSET \
 394         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 395 #define CONFIG_SYS_INIT_SP_ADDR \
 396         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 397
 398 #ifdef CONFIG_SPL_BUILD
 399 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 400 #else
 401 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 402 #endif
 403
 404 /*
 405  * Environment
 406  */
 407
 408 #include <asm/fsl_secure_boot.h>
 409 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 410
 411 #endif