include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_DEEP_SLEEP
  13
  14 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  15 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  16
  17 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  18 #define CONFIG_QIXIS_I2C_ACCESS
  19 #endif
  20
  21 #ifdef CONFIG_SD_BOOT
  22 #define CONFIG_SPL_MAX_SIZE             0x1a000
  23 #define CONFIG_SPL_STACK                0x1001d000
  24 #define CONFIG_SPL_PAD_TO               0x1c000
  25
  26 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  27                 CONFIG_SYS_MONITOR_LEN)
  28 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  29 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  30 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  31 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  32 #endif
  33
  34 #ifdef CONFIG_NAND_BOOT
  35 #define CONFIG_SPL_MAX_SIZE             0x1a000
  36 #define CONFIG_SPL_STACK                0x1001d000
  37 #define CONFIG_SPL_PAD_TO               0x1c000
  38
  39 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  40 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  41 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  42
  43 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  44 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  45 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  46 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  47 #define CONFIG_SYS_MONITOR_LEN          0x80000
  48 #endif
  49
  50 #define SPD_EEPROM_ADDRESS              0x51
  51 #define CONFIG_SYS_SPD_BUS_NUM          0
  52
  53 #ifndef CONFIG_SYS_FSL_DDR4
  54 #define CONFIG_SYS_DDR_RAW_TIMING
  55 #endif
  56 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  57 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  58
  59 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  60 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  61
  62 #ifdef CONFIG_DDR_ECC
  63 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  64 #endif
  65
  66 /*
  67  * IFC Definitions
  68  */
  69 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  70 #define CONFIG_SYS_FLASH_BASE           0x60000000
  71 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  72
  73 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  74 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  75                                 CSPR_PORT_SIZE_16 | \
  76                                 CSPR_MSEL_NOR | \
  77                                 CSPR_V)
  78 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  79 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  80                                 + 0x8000000) | \
  81                                 CSPR_PORT_SIZE_16 | \
  82                                 CSPR_MSEL_NOR | \
  83                                 CSPR_V)
  84 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  85
  86 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  87                                         CSOR_NOR_TRHZ_80)
  88 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  89                                         FTIM0_NOR_TEADC(0x5) | \
  90                                         FTIM0_NOR_TEAHC(0x5))
  91 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  92                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  93                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  94 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  95                                         FTIM2_NOR_TCH(0x4) | \
  96                                         FTIM2_NOR_TWPH(0xe) | \
  97                                         FTIM2_NOR_TWP(0x1c))
  98 #define CONFIG_SYS_NOR_FTIM3            0
  99
 100 #define CONFIG_SYS_FLASH_QUIET_TEST
 101 #define CONFIG_FLASH_SHOW_PROGRESS      45
 102 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 103 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 104
 105 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 106 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 107 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 108 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 109
 110 #define CONFIG_SYS_FLASH_EMPTY_INFO
 111 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 112                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 113
 114 /*
 115  * NAND Flash Definitions
 116  */
 117
 118 #define CONFIG_SYS_NAND_BASE            0x7e800000
 119 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 120
 121 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 122
 123 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 124                                 | CSPR_PORT_SIZE_8      \
 125                                 | CSPR_MSEL_NAND        \
 126                                 | CSPR_V)
 127 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 128 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 129                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 130                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 131                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 132                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 133                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 134                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 135
 136 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 137                                         FTIM0_NAND_TWP(0x18)   | \
 138                                         FTIM0_NAND_TWCHT(0x7) | \
 139                                         FTIM0_NAND_TWH(0xa))
 140 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 141                                         FTIM1_NAND_TWBE(0x39)  | \
 142                                         FTIM1_NAND_TRR(0xe)   | \
 143                                         FTIM1_NAND_TRP(0x18))
 144 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 145                                         FTIM2_NAND_TREH(0xa) | \
 146                                         FTIM2_NAND_TWHRE(0x1e))
 147 #define CONFIG_SYS_NAND_FTIM3           0x0
 148
 149 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 150 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 151 #endif
 152
 153 /*
 154  * QIXIS Definitions
 155  */
 156 #define CONFIG_FSL_QIXIS
 157
 158 #ifdef CONFIG_FSL_QIXIS
 159 #define QIXIS_BASE                      0x7fb00000
 160 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 161 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 162 #define QIXIS_LBMAP_SWITCH              6
 163 #define QIXIS_LBMAP_MASK                0x0f
 164 #define QIXIS_LBMAP_SHIFT               0
 165 #define QIXIS_LBMAP_DFLTBANK            0x00
 166 #define QIXIS_LBMAP_ALTBANK             0x04
 167 #define QIXIS_PWR_CTL                   0x21
 168 #define QIXIS_PWR_CTL_POWEROFF          0x80
 169 #define QIXIS_RST_CTL_RESET             0x44
 170 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 171 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 172 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 173 #define QIXIS_CTL_SYS                   0x5
 174 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 175 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 176 #define QIXIS_RST_FORCE_3               0x45
 177 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 178 #define QIXIS_PWR_CTL2                  0x21
 179 #define QIXIS_PWR_CTL2_PCTL             0x2
 180
 181 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 182 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 183                                         CSPR_PORT_SIZE_8 | \
 184                                         CSPR_MSEL_GPCM | \
 185                                         CSPR_V)
 186 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 187 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 188                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 189                                         CSOR_NOR_TRHZ_80)
 190
 191 /*
 192  * QIXIS Timing parameters for IFC GPCM
 193  */
 194 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 195                                         FTIM0_GPCM_TEADC(0xe) | \
 196                                         FTIM0_GPCM_TEAHC(0xe))
 197 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 198                                         FTIM1_GPCM_TRAD(0x1f))
 199 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 200                                         FTIM2_GPCM_TCH(0xe) | \
 201                                         FTIM2_GPCM_TWP(0xf0))
 202 #define CONFIG_SYS_FPGA_FTIM3           0x0
 203 #endif
 204
 205 #if defined(CONFIG_NAND_BOOT)
 206 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 207 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 208 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 209 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 210 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 211 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 212 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 213 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 214 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 215 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 216 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 217 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 218 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 219 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 220 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 221 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 222 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 223 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 224 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 225 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 226 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 227 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 228 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 229 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 230 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 231 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 232 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 233 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 234 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 235 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 236 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 237 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 238 #else
 239 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 240 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 241 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 242 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 243 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 244 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 245 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 246 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 247 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 248 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 249 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 250 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 251 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 252 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 253 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 254 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 255 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 256 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 257 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 258 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 259 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 260 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 261 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 262 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 263 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 264 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 265 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 266 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 267 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 268 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 269 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 270 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 271 #endif
 272
 273 /*
 274  * Serial Port
 275  */
 276 #ifdef CONFIG_LPUART
 277 #define CONFIG_LPUART_32B_REG
 278 #else
 279 #define CONFIG_SYS_NS16550_SERIAL
 280 #ifndef CONFIG_DM_SERIAL
 281 #define CONFIG_SYS_NS16550_REG_SIZE     1
 282 #endif
 283 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 284 #endif
 285
 286 /*
 287  * I2C
 288  */
 289
 290 /* GPIO */
 291
 292 /* EEPROM */
 293 #define CONFIG_SYS_I2C_EEPROM_NXID
 294 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 295
 296 /*
 297  * I2C bus multiplexer
 298  */
 299 #define I2C_MUX_PCA_ADDR_PRI            0x77
 300 #define I2C_MUX_CH_DEFAULT              0x8
 301 #define I2C_MUX_CH_CH7301               0xC
 302
 303 /*
 304  * MMC
 305  */
 306
 307 /*
 308  * Video
 309  */
 310 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 311 #define CONFIG_VIDEO_BMP_LOGO
 312
 313 #define CONFIG_FSL_DIU_CH7301
 314 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 315 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
 316 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 317 #endif
 318
 319 /*
 320  * eTSEC
 321  */
 322
 323 #ifdef CONFIG_TSEC_ENET
 324 #define CONFIG_MII_DEFAULT_TSEC         3
 325 #define CONFIG_TSEC1                    1
 326 #define CONFIG_TSEC1_NAME               "eTSEC1"
 327 #define CONFIG_TSEC2                    1
 328 #define CONFIG_TSEC2_NAME               "eTSEC2"
 329 #define CONFIG_TSEC3                    1
 330 #define CONFIG_TSEC3_NAME               "eTSEC3"
 331
 332 #define TSEC1_PHY_ADDR                  1
 333 #define TSEC2_PHY_ADDR                  2
 334 #define TSEC3_PHY_ADDR                  3
 335
 336 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 337 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 338 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 339
 340 #define TSEC1_PHYIDX                    0
 341 #define TSEC2_PHYIDX                    0
 342 #define TSEC3_PHYIDX                    0
 343
 344 #define CONFIG_ETHPRIME                 "eTSEC1"
 345
 346 #define CONFIG_HAS_ETH0
 347 #define CONFIG_HAS_ETH1
 348 #define CONFIG_HAS_ETH2
 349
 350 #define CONFIG_FSL_SGMII_RISER          1
 351 #define SGMII_RISER_PHY_OFFSET          0x1b
 352
 353 #ifdef CONFIG_FSL_SGMII_RISER
 354 #define CONFIG_SYS_TBIPA_VALUE          8
 355 #endif
 356
 357 #endif
 358
 359 /* PCIe */
 360 #define CONFIG_PCIE1            /* PCIE controller 1 */
 361 #define CONFIG_PCIE2            /* PCIE controller 2 */
 362
 363 #ifdef CONFIG_PCI
 364 #define CONFIG_PCI_SCAN_SHOW
 365 #endif
 366
 367 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 368 #define CONFIG_LAYERSCAPE_NS_ACCESS
 369 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 370 #define COUNTER_FREQUENCY               12500000
 371
 372 #define CONFIG_HWCONFIG
 373 #define HWCONFIG_BUFFER_SIZE            256
 374
 375 #define CONFIG_FSL_DEVICE_DISABLE
 376
 377 #ifdef CONFIG_LPUART
 378 #define CONFIG_EXTRA_ENV_SETTINGS       \
 379         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 380         "initrd_high=0xffffffff\0"      \
 381         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 382 #else
 383 #define CONFIG_EXTRA_ENV_SETTINGS       \
 384         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 385         "initrd_high=0xffffffff\0"      \
 386         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 387 #endif
 388
 389 /*
 390  * Miscellaneous configurable options
 391  */
 392 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 393
 394 #define CONFIG_LS102XA_STREAM_ID
 395
 396 #define CONFIG_SYS_INIT_SP_OFFSET \
 397         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 398 #define CONFIG_SYS_INIT_SP_ADDR \
 399         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 400
 401 #ifdef CONFIG_SPL_BUILD
 402 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 403 #else
 404 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 405 #endif
 406
 407 /*
 408  * Environment
 409  */
 410
 411 #include <asm/fsl_secure_boot.h>
 412 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 413
 414 #endif