include/configs/ls1021aqds.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_LS102XA
  11
  12 #define CONFIG_ARMV7_PSCI
  13 #define CONFIG_ARMV7_PSCI_NR_CPUS       CONFIG_MAX_CPUS
  14
  15 #define CONFIG_SYS_FSL_CLK
  16
  17 #define CONFIG_DISPLAY_CPUINFO
  18 #define CONFIG_DISPLAY_BOARDINFO
  19
  20 #define CONFIG_SKIP_LOWLEVEL_INIT
  21 #define CONFIG_BOARD_EARLY_INIT_F
  22
  23 #define CONFIG_DEEP_SLEEP
  24 #if defined(CONFIG_DEEP_SLEEP)
  25 #define CONFIG_SILENT_CONSOLE
  26 #endif
  27
  28 /*
  29  * Size of malloc() pool
  30  */
  31 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  32
  33 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  34 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  35
  36 /*
  37  * Generic Timer Definitions
  38  */
  39 #define GENERIC_TIMER_CLK               12500000
  40
  41 #ifndef __ASSEMBLY__
  42 unsigned long get_board_sys_clk(void);
  43 unsigned long get_board_ddr_clk(void);
  44 #endif
  45
  46 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  47 #define CONFIG_SYS_CLK_FREQ             100000000
  48 #define CONFIG_DDR_CLK_FREQ             100000000
  49 #define CONFIG_QIXIS_I2C_ACCESS
  50 #else
  51 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  52 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  53 #endif
  54
  55 #ifdef CONFIG_RAMBOOT_PBL
  56 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021aqds/ls102xa_pbi.cfg
  57 #endif
  58
  59 #ifdef CONFIG_SD_BOOT
  60 #ifdef CONFIG_SD_BOOT_QSPI
  61 #define CONFIG_SYS_FSL_PBL_RCW  \
  62         board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
  63 #else
  64 #define CONFIG_SYS_FSL_PBL_RCW  \
  65         board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
  66 #endif
  67 #define CONFIG_SPL_FRAMEWORK
  68 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
  69 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  70 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  71 #define CONFIG_SPL_ENV_SUPPORT
  72 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  73 #define CONFIG_SPL_I2C_SUPPORT
  74 #define CONFIG_SPL_WATCHDOG_SUPPORT
  75 #define CONFIG_SPL_SERIAL_SUPPORT
  76 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  77 #define CONFIG_SPL_MMC_SUPPORT
  78 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0xe8
  79 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x600
  80
  81 #define CONFIG_SPL_TEXT_BASE            0x10000000
  82 #define CONFIG_SPL_MAX_SIZE             0x1a000
  83 #define CONFIG_SPL_STACK                0x1001d000
  84 #define CONFIG_SPL_PAD_TO               0x1c000
  85 #define CONFIG_SYS_TEXT_BASE            0x82000000
  86
  87 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  88                 CONFIG_SYS_MONITOR_LEN)
  89 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  90 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  91 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  92 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  93 #endif
  94
  95 #ifdef CONFIG_QSPI_BOOT
  96 #define CONFIG_SYS_TEXT_BASE            0x40010000
  97 #endif
  98
  99 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 100 #define CONFIG_SYS_NO_FLASH
 101 #endif
 102
 103 #ifdef CONFIG_NAND_BOOT
 104 #define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
 105 #define CONFIG_SPL_FRAMEWORK
 106 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
 107 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 108 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 109 #define CONFIG_SPL_ENV_SUPPORT
 110 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 111 #define CONFIG_SPL_I2C_SUPPORT
 112 #define CONFIG_SPL_WATCHDOG_SUPPORT
 113 #define CONFIG_SPL_SERIAL_SUPPORT
 114 #define CONFIG_SPL_NAND_SUPPORT
 115 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 116
 117 #define CONFIG_SPL_TEXT_BASE            0x10000000
 118 #define CONFIG_SPL_MAX_SIZE             0x1a000
 119 #define CONFIG_SPL_STACK                0x1001d000
 120 #define CONFIG_SPL_PAD_TO               0x1c000
 121 #define CONFIG_SYS_TEXT_BASE            0x82000000
 122
 123 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
 124 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 125 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 126 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 127 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 128
 129 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
 130 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 131 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 132 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 133 #define CONFIG_SYS_MONITOR_LEN          0x80000
 134 #endif
 135
 136 #ifndef CONFIG_SYS_TEXT_BASE
 137 #define CONFIG_SYS_TEXT_BASE            0x60100000
 138 #endif
 139
 140 #define CONFIG_NR_DRAM_BANKS            1
 141
 142 #define CONFIG_DDR_SPD
 143 #define SPD_EEPROM_ADDRESS              0x51
 144 #define CONFIG_SYS_SPD_BUS_NUM          0
 145
 146 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
 147 #ifndef CONFIG_SYS_FSL_DDR4
 148 #define CONFIG_SYS_FSL_DDR3             /* Use DDR3 memory */
 149 #define CONFIG_SYS_DDR_RAW_TIMING
 150 #endif
 151 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 152 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 153
 154 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
 155 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 156
 157 #define CONFIG_DDR_ECC
 158 #ifdef CONFIG_DDR_ECC
 159 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 160 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 161 #endif
 162
 163 #define CONFIG_SYS_HAS_SERDES
 164
 165 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
 166
 167 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 168         !defined(CONFIG_QSPI_BOOT)
 169 #define CONFIG_U_QE
 170 #endif
 171
 172 /*
 173  * IFC Definitions
 174  */
 175 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 176 #define CONFIG_FSL_IFC
 177 #define CONFIG_SYS_FLASH_BASE           0x60000000
 178 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 179
 180 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 181 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 182                                 CSPR_PORT_SIZE_16 | \
 183                                 CSPR_MSEL_NOR | \
 184                                 CSPR_V)
 185 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 186 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 187                                 + 0x8000000) | \
 188                                 CSPR_PORT_SIZE_16 | \
 189                                 CSPR_MSEL_NOR | \
 190                                 CSPR_V)
 191 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 192
 193 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 194                                         CSOR_NOR_TRHZ_80)
 195 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 196                                         FTIM0_NOR_TEADC(0x5) | \
 197                                         FTIM0_NOR_TEAHC(0x5))
 198 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 199                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 200                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 201 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 202                                         FTIM2_NOR_TCH(0x4) | \
 203                                         FTIM2_NOR_TWPH(0xe) | \
 204                                         FTIM2_NOR_TWP(0x1c))
 205 #define CONFIG_SYS_NOR_FTIM3            0
 206
 207 #define CONFIG_FLASH_CFI_DRIVER
 208 #define CONFIG_SYS_FLASH_CFI
 209 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 210 #define CONFIG_SYS_FLASH_QUIET_TEST
 211 #define CONFIG_FLASH_SHOW_PROGRESS      45
 212 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 213 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 214
 215 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 216 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 217 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 218 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 219
 220 #define CONFIG_SYS_FLASH_EMPTY_INFO
 221 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 222                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 223
 224 /*
 225  * NAND Flash Definitions
 226  */
 227 #define CONFIG_NAND_FSL_IFC
 228
 229 #define CONFIG_SYS_NAND_BASE            0x7e800000
 230 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 231
 232 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 233
 234 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 235                                 | CSPR_PORT_SIZE_8      \
 236                                 | CSPR_MSEL_NAND        \
 237                                 | CSPR_V)
 238 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 239 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 240                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 241                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 242                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 243                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 244                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 245                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 246
 247 #define CONFIG_SYS_NAND_ONFI_DETECTION
 248
 249 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 250                                         FTIM0_NAND_TWP(0x18)   | \
 251                                         FTIM0_NAND_TWCHT(0x7) | \
 252                                         FTIM0_NAND_TWH(0xa))
 253 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 254                                         FTIM1_NAND_TWBE(0x39)  | \
 255                                         FTIM1_NAND_TRR(0xe)   | \
 256                                         FTIM1_NAND_TRP(0x18))
 257 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 258                                         FTIM2_NAND_TREH(0xa) | \
 259                                         FTIM2_NAND_TWHRE(0x1e))
 260 #define CONFIG_SYS_NAND_FTIM3           0x0
 261
 262 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 263 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 264 #define CONFIG_CMD_NAND
 265
 266 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 267 #endif
 268
 269 /*
 270  * QIXIS Definitions
 271  */
 272 #define CONFIG_FSL_QIXIS
 273
 274 #ifdef CONFIG_FSL_QIXIS
 275 #define QIXIS_BASE                      0x7fb00000
 276 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 277 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 278 #define QIXIS_LBMAP_SWITCH              6
 279 #define QIXIS_LBMAP_MASK                0x0f
 280 #define QIXIS_LBMAP_SHIFT               0
 281 #define QIXIS_LBMAP_DFLTBANK            0x00
 282 #define QIXIS_LBMAP_ALTBANK             0x04
 283 #define QIXIS_RST_CTL_RESET             0x44
 284 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 285 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 286 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 287
 288 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 289 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 290                                         CSPR_PORT_SIZE_8 | \
 291                                         CSPR_MSEL_GPCM | \
 292                                         CSPR_V)
 293 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 294 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 295                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 296                                         CSOR_NOR_TRHZ_80)
 297
 298 /*
 299  * QIXIS Timing parameters for IFC GPCM
 300  */
 301 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 302                                         FTIM0_GPCM_TEADC(0xe) | \
 303                                         FTIM0_GPCM_TEAHC(0xe))
 304 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 305                                         FTIM1_GPCM_TRAD(0x1f))
 306 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 307                                         FTIM2_GPCM_TCH(0xe) | \
 308                                         FTIM2_GPCM_TWP(0xf0))
 309 #define CONFIG_SYS_FPGA_FTIM3           0x0
 310 #endif
 311
 312 #if defined(CONFIG_NAND_BOOT)
 313 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 314 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 315 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 316 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 317 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 318 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 319 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 320 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 321 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 322 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 323 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 324 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 325 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 326 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 327 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 328 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 329 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 330 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 331 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 332 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 333 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 334 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 335 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 336 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 337 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 338 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 339 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 340 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 341 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 342 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 343 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 344 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 345 #else
 346 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 347 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 348 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 349 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 350 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 351 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 352 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 353 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 354 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 355 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 356 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 357 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 358 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 359 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 360 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 361 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 362 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 363 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 364 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 365 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 366 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 367 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 368 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 369 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 370 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 371 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 372 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 373 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 374 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 375 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 376 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 377 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 378 #endif
 379
 380 /*
 381  * Serial Port
 382  */
 383 #ifdef CONFIG_LPUART
 384 #define CONFIG_LPUART_32B_REG
 385 #else
 386 #define CONFIG_CONS_INDEX               1
 387 #define CONFIG_SYS_NS16550_SERIAL
 388 #ifndef CONFIG_DM_SERIAL
 389 #define CONFIG_SYS_NS16550_REG_SIZE     1
 390 #endif
 391 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 392 #endif
 393
 394 #define CONFIG_BAUDRATE                 115200
 395
 396 /*
 397  * I2C
 398  */
 399 #define CONFIG_SYS_I2C
 400 #define CONFIG_SYS_I2C_MXC
 401 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 402 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 403 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 404
 405 /*
 406  * I2C bus multiplexer
 407  */
 408 #define I2C_MUX_PCA_ADDR_PRI            0x77
 409 #define I2C_MUX_CH_DEFAULT              0x8
 410 #define I2C_MUX_CH_CH7301               0xC
 411
 412 /*
 413  * MMC
 414  */
 415 #define CONFIG_MMC
 416 #define CONFIG_FSL_ESDHC
 417 #define CONFIG_GENERIC_MMC
 418
 419 #define CONFIG_DOS_PARTITION
 420
 421 /* SPI */
 422 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 423 /* QSPI */
 424 #define QSPI0_AMBA_BASE                 0x40000000
 425 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 426 #define FSL_QSPI_FLASH_NUM              2
 427
 428 /* DSPI */
 429
 430 /* DM SPI */
 431 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 432 #define CONFIG_DM_SPI_FLASH
 433 #define CONFIG_SPI_FLASH_DATAFLASH
 434 #endif
 435 #endif
 436
 437 /*
 438  * USB
 439  */
 440 /* EHCI Support - disbaled by default */
 441 /*#define CONFIG_HAS_FSL_DR_USB*/
 442
 443 #ifdef CONFIG_HAS_FSL_DR_USB
 444 #define CONFIG_USB_EHCI
 445 #define CONFIG_USB_EHCI_FSL
 446 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 447 #endif
 448
 449 /*XHCI Support - enabled by default*/
 450 #define CONFIG_HAS_FSL_XHCI_USB
 451
 452 #ifdef CONFIG_HAS_FSL_XHCI_USB
 453 #define CONFIG_USB_XHCI_FSL
 454 #define CONFIG_USB_MAX_CONTROLLER_COUNT         1
 455 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 456 #endif
 457
 458 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
 459 #define CONFIG_USB_STORAGE
 460 #endif
 461
 462 /*
 463  * Video
 464  */
 465 #define CONFIG_FSL_DCU_FB
 466
 467 #ifdef CONFIG_FSL_DCU_FB
 468 #define CONFIG_VIDEO
 469 #define CONFIG_CMD_BMP
 470 #define CONFIG_CFB_CONSOLE
 471 #define CONFIG_VGA_AS_SINGLE_DEVICE
 472 #define CONFIG_VIDEO_LOGO
 473 #define CONFIG_VIDEO_BMP_LOGO
 474 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 475
 476 #define CONFIG_FSL_DIU_CH7301
 477 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 478 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
 479 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 480 #endif
 481
 482 /*
 483  * eTSEC
 484  */
 485 #define CONFIG_TSEC_ENET
 486
 487 #ifdef CONFIG_TSEC_ENET
 488 #define CONFIG_MII
 489 #define CONFIG_MII_DEFAULT_TSEC         3
 490 #define CONFIG_TSEC1                    1
 491 #define CONFIG_TSEC1_NAME               "eTSEC1"
 492 #define CONFIG_TSEC2                    1
 493 #define CONFIG_TSEC2_NAME               "eTSEC2"
 494 #define CONFIG_TSEC3                    1
 495 #define CONFIG_TSEC3_NAME               "eTSEC3"
 496
 497 #define TSEC1_PHY_ADDR                  1
 498 #define TSEC2_PHY_ADDR                  2
 499 #define TSEC3_PHY_ADDR                  3
 500
 501 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 502 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 503 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 504
 505 #define TSEC1_PHYIDX                    0
 506 #define TSEC2_PHYIDX                    0
 507 #define TSEC3_PHYIDX                    0
 508
 509 #define CONFIG_ETHPRIME                 "eTSEC1"
 510
 511 #define CONFIG_PHY_GIGE
 512 #define CONFIG_PHYLIB
 513 #define CONFIG_PHY_REALTEK
 514
 515 #define CONFIG_HAS_ETH0
 516 #define CONFIG_HAS_ETH1
 517 #define CONFIG_HAS_ETH2
 518
 519 #define CONFIG_FSL_SGMII_RISER          1
 520 #define SGMII_RISER_PHY_OFFSET          0x1b
 521
 522 #ifdef CONFIG_FSL_SGMII_RISER
 523 #define CONFIG_SYS_TBIPA_VALUE          8
 524 #endif
 525
 526 #endif
 527
 528 /* PCIe */
 529 #define CONFIG_PCI              /* Enable PCI/PCIE */
 530 #define CONFIG_PCIE1            /* PCIE controller 1 */
 531 #define CONFIG_PCIE2            /* PCIE controller 2 */
 532 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 533 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 534
 535 #define CONFIG_SYS_PCI_64BIT
 536
 537 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF   0x00000000
 538 #define CONFIG_SYS_PCIE_CFG0_SIZE       0x00001000      /* 4k */
 539 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF   0x00001000
 540 #define CONFIG_SYS_PCIE_CFG1_SIZE       0x00001000      /* 4k */
 541
 542 #define CONFIG_SYS_PCIE_IO_BUS          0x00000000
 543 #define CONFIG_SYS_PCIE_IO_PHYS_OFF     0x00010000
 544 #define CONFIG_SYS_PCIE_IO_SIZE         0x00010000      /* 64k */
 545
 546 #define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
 547 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
 548 #define CONFIG_SYS_PCIE_MEM_SIZE        0x08000000      /* 128M */
 549
 550 #ifdef CONFIG_PCI
 551 #define CONFIG_PCI_PNP
 552 #define CONFIG_PCI_SCAN_SHOW
 553 #define CONFIG_CMD_PCI
 554 #endif
 555
 556 #define CONFIG_CMDLINE_TAG
 557 #define CONFIG_CMDLINE_EDITING
 558
 559 #define CONFIG_ARMV7_NONSEC
 560 #define CONFIG_ARMV7_VIRT
 561 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 562 #define CONFIG_LAYERSCAPE_NS_ACCESS
 563 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 564 #define CONFIG_TIMER_CLK_FREQ           12500000
 565
 566 #define CONFIG_HWCONFIG
 567 #define HWCONFIG_BUFFER_SIZE            256
 568
 569 #define CONFIG_FSL_DEVICE_DISABLE
 570
 571
 572 #define CONFIG_SYS_QE_FW_ADDR     0x600c0000
 573
 574 #ifdef CONFIG_LPUART
 575 #define CONFIG_EXTRA_ENV_SETTINGS       \
 576         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 577         "fdt_high=0xffffffff\0"         \
 578         "initrd_high=0xffffffff\0"      \
 579         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 580 #else
 581 #define CONFIG_EXTRA_ENV_SETTINGS       \
 582         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 583         "fdt_high=0xffffffff\0"         \
 584         "initrd_high=0xffffffff\0"      \
 585         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 586 #endif
 587
 588 /*
 589  * Miscellaneous configurable options
 590  */
 591 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 592 #define CONFIG_AUTO_COMPLETE
 593 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 594 #define CONFIG_SYS_PBSIZE               \
 595                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 596 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 597 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 598
 599 #define CONFIG_SYS_MEMTEST_START        0x80000000
 600 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 601
 602 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 603
 604 #define CONFIG_LS102XA_STREAM_ID
 605
 606 /*
 607  * Stack sizes
 608  * The stack sizes are set up in start.S using the settings below
 609  */
 610 #define CONFIG_STACKSIZE                (30 * 1024)
 611
 612 #define CONFIG_SYS_INIT_SP_OFFSET \
 613         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 614 #define CONFIG_SYS_INIT_SP_ADDR \
 615         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 616
 617 #ifdef CONFIG_SPL_BUILD
 618 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 619 #else
 620 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 621 #endif
 622
 623 /*
 624  * Environment
 625  */
 626 #define CONFIG_ENV_OVERWRITE
 627
 628 #if defined(CONFIG_SD_BOOT)
 629 #define CONFIG_ENV_OFFSET               0x100000
 630 #define CONFIG_ENV_IS_IN_MMC
 631 #define CONFIG_SYS_MMC_ENV_DEV          0
 632 #define CONFIG_ENV_SIZE                 0x2000
 633 #elif defined(CONFIG_QSPI_BOOT)
 634 #define CONFIG_ENV_IS_IN_SPI_FLASH
 635 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 636 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 637 #define CONFIG_ENV_SECT_SIZE            0x10000
 638 #elif defined(CONFIG_NAND_BOOT)
 639 #define CONFIG_ENV_IS_IN_NAND
 640 #define CONFIG_ENV_SIZE                 0x2000
 641 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 642 #else
 643 #define CONFIG_ENV_IS_IN_FLASH
 644 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 645 #define CONFIG_ENV_SIZE                 0x2000
 646 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 647 #endif
 648
 649 #define CONFIG_MISC_INIT_R
 650
 651 /* Hash command with SHA acceleration supported in hardware */
 652 #ifdef CONFIG_FSL_CAAM
 653 #define CONFIG_CMD_HASH
 654 #define CONFIG_SHA_HW_ACCEL
 655 #endif
 656
 657 #include <asm/fsl_secure_boot.h>
 658 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 659
 660 #endif