include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  11
  12 #define CONFIG_SYS_FSL_CLK
  13
  14 #define CONFIG_SKIP_LOWLEVEL_INIT
  15
  16 #define CONFIG_DEEP_SLEEP
  17
  18 /*
  19  * Size of malloc() pool
  20  */
  21 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  22
  23 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  24 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  25
  26 #ifndef __ASSEMBLY__
  27 unsigned long get_board_sys_clk(void);
  28 unsigned long get_board_ddr_clk(void);
  29 #endif
  30
  31 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  32 #define CONFIG_SYS_CLK_FREQ             100000000
  33 #define CONFIG_DDR_CLK_FREQ             100000000
  34 #define CONFIG_QIXIS_I2C_ACCESS
  35 #else
  36 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  37 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  38 #endif
  39
  40 #ifdef CONFIG_RAMBOOT_PBL
  41 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021aqds/ls102xa_pbi.cfg
  42 #endif
  43
  44 #ifdef CONFIG_SD_BOOT
  45 #ifdef CONFIG_SD_BOOT_QSPI
  46 #define CONFIG_SYS_FSL_PBL_RCW  \
  47         board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
  48 #else
  49 #define CONFIG_SYS_FSL_PBL_RCW  \
  50         board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
  51 #endif
  52
  53 #define CONFIG_SPL_MAX_SIZE             0x1a000
  54 #define CONFIG_SPL_STACK                0x1001d000
  55 #define CONFIG_SPL_PAD_TO               0x1c000
  56
  57 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  58                 CONFIG_SYS_MONITOR_LEN)
  59 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  60 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  61 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  62 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  63 #endif
  64
  65 #ifdef CONFIG_NAND_BOOT
  66 #define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
  67
  68 #define CONFIG_SPL_MAX_SIZE             0x1a000
  69 #define CONFIG_SPL_STACK                0x1001d000
  70 #define CONFIG_SPL_PAD_TO               0x1c000
  71
  72 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  73 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
  74 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
  75 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  76 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  77
  78 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  79 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  80 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  81 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  82 #define CONFIG_SYS_MONITOR_LEN          0x80000
  83 #endif
  84
  85 #define CONFIG_DDR_SPD
  86 #define SPD_EEPROM_ADDRESS              0x51
  87 #define CONFIG_SYS_SPD_BUS_NUM          0
  88
  89 #ifndef CONFIG_SYS_FSL_DDR4
  90 #define CONFIG_SYS_DDR_RAW_TIMING
  91 #endif
  92 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  93 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  94
  95 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  96 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  97
  98 #define CONFIG_DDR_ECC
  99 #ifdef CONFIG_DDR_ECC
 100 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 101 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 102 #endif
 103
 104 /*
 105  * IFC Definitions
 106  */
 107 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 108 #define CONFIG_FSL_IFC
 109 #define CONFIG_SYS_FLASH_BASE           0x60000000
 110 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 111
 112 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 113 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 114                                 CSPR_PORT_SIZE_16 | \
 115                                 CSPR_MSEL_NOR | \
 116                                 CSPR_V)
 117 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 118 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 119                                 + 0x8000000) | \
 120                                 CSPR_PORT_SIZE_16 | \
 121                                 CSPR_MSEL_NOR | \
 122                                 CSPR_V)
 123 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 124
 125 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 126                                         CSOR_NOR_TRHZ_80)
 127 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 128                                         FTIM0_NOR_TEADC(0x5) | \
 129                                         FTIM0_NOR_TEAHC(0x5))
 130 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 131                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 132                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 133 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 134                                         FTIM2_NOR_TCH(0x4) | \
 135                                         FTIM2_NOR_TWPH(0xe) | \
 136                                         FTIM2_NOR_TWP(0x1c))
 137 #define CONFIG_SYS_NOR_FTIM3            0
 138
 139 #define CONFIG_SYS_FLASH_QUIET_TEST
 140 #define CONFIG_FLASH_SHOW_PROGRESS      45
 141 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 142 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 143
 144 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 145 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 146 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 147 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 148
 149 #define CONFIG_SYS_FLASH_EMPTY_INFO
 150 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 151                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 152
 153 /*
 154  * NAND Flash Definitions
 155  */
 156 #define CONFIG_NAND_FSL_IFC
 157
 158 #define CONFIG_SYS_NAND_BASE            0x7e800000
 159 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 160
 161 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 162
 163 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 164                                 | CSPR_PORT_SIZE_8      \
 165                                 | CSPR_MSEL_NAND        \
 166                                 | CSPR_V)
 167 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 168 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 169                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 170                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 171                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 172                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 173                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 174                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 175
 176 #define CONFIG_SYS_NAND_ONFI_DETECTION
 177
 178 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 179                                         FTIM0_NAND_TWP(0x18)   | \
 180                                         FTIM0_NAND_TWCHT(0x7) | \
 181                                         FTIM0_NAND_TWH(0xa))
 182 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 183                                         FTIM1_NAND_TWBE(0x39)  | \
 184                                         FTIM1_NAND_TRR(0xe)   | \
 185                                         FTIM1_NAND_TRP(0x18))
 186 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 187                                         FTIM2_NAND_TREH(0xa) | \
 188                                         FTIM2_NAND_TWHRE(0x1e))
 189 #define CONFIG_SYS_NAND_FTIM3           0x0
 190
 191 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 192 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 193
 194 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 195 #endif
 196
 197 /*
 198  * QIXIS Definitions
 199  */
 200 #define CONFIG_FSL_QIXIS
 201
 202 #ifdef CONFIG_FSL_QIXIS
 203 #define QIXIS_BASE                      0x7fb00000
 204 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 205 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 206 #define QIXIS_LBMAP_SWITCH              6
 207 #define QIXIS_LBMAP_MASK                0x0f
 208 #define QIXIS_LBMAP_SHIFT               0
 209 #define QIXIS_LBMAP_DFLTBANK            0x00
 210 #define QIXIS_LBMAP_ALTBANK             0x04
 211 #define QIXIS_PWR_CTL                   0x21
 212 #define QIXIS_PWR_CTL_POWEROFF          0x80
 213 #define QIXIS_RST_CTL_RESET             0x44
 214 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 215 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 216 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 217 #define QIXIS_CTL_SYS                   0x5
 218 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 219 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 220 #define QIXIS_RST_FORCE_3               0x45
 221 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 222 #define QIXIS_PWR_CTL2                  0x21
 223 #define QIXIS_PWR_CTL2_PCTL             0x2
 224
 225 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 226 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 227                                         CSPR_PORT_SIZE_8 | \
 228                                         CSPR_MSEL_GPCM | \
 229                                         CSPR_V)
 230 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 231 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 232                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 233                                         CSOR_NOR_TRHZ_80)
 234
 235 /*
 236  * QIXIS Timing parameters for IFC GPCM
 237  */
 238 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 239                                         FTIM0_GPCM_TEADC(0xe) | \
 240                                         FTIM0_GPCM_TEAHC(0xe))
 241 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 242                                         FTIM1_GPCM_TRAD(0x1f))
 243 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 244                                         FTIM2_GPCM_TCH(0xe) | \
 245                                         FTIM2_GPCM_TWP(0xf0))
 246 #define CONFIG_SYS_FPGA_FTIM3           0x0
 247 #endif
 248
 249 #if defined(CONFIG_NAND_BOOT)
 250 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 251 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 252 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 253 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 254 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 255 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 256 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 257 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 258 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 259 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 260 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 261 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 262 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 263 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 264 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 265 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 266 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 267 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 268 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 269 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 270 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 271 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 272 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 273 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 274 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 275 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 276 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 277 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 278 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 279 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 280 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 281 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 282 #else
 283 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 284 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 285 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 286 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 287 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 288 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 289 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 290 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 291 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 292 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 293 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 294 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 295 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 296 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 297 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 298 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 299 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 300 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 301 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 302 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 303 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 304 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 305 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 306 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 307 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 308 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 309 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 310 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 311 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 312 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 313 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 314 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 315 #endif
 316
 317 /*
 318  * Serial Port
 319  */
 320 #ifdef CONFIG_LPUART
 321 #define CONFIG_LPUART_32B_REG
 322 #else
 323 #define CONFIG_SYS_NS16550_SERIAL
 324 #ifndef CONFIG_DM_SERIAL
 325 #define CONFIG_SYS_NS16550_REG_SIZE     1
 326 #endif
 327 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 328 #endif
 329
 330 /*
 331  * I2C
 332  */
 333 #if !CONFIG_IS_ENABLED(DM_I2C)
 334 #else
 335 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 336 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
 337 #endif
 338 #define CONFIG_SYS_I2C_MXC
 339 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 340 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 341 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 342
 343 /* GPIO */
 344 #ifdef CONFIG_DM_GPIO
 345 #ifndef CONFIG_MPC8XXX_GPIO
 346 #define CONFIG_MPC8XXX_GPIO
 347 #endif
 348 #endif
 349
 350 /* EEPROM */
 351 #define CONFIG_SYS_I2C_EEPROM_NXID
 352 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 353
 354 /*
 355  * I2C bus multiplexer
 356  */
 357 #define I2C_MUX_PCA_ADDR_PRI            0x77
 358 #define I2C_MUX_CH_DEFAULT              0x8
 359 #define I2C_MUX_CH_CH7301               0xC
 360
 361 /*
 362  * MMC
 363  */
 364
 365 /*
 366  * Video
 367  */
 368 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 369 #define CONFIG_VIDEO_LOGO
 370 #define CONFIG_VIDEO_BMP_LOGO
 371
 372 #define CONFIG_FSL_DIU_CH7301
 373 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 374 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
 375 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 376 #endif
 377
 378 /*
 379  * eTSEC
 380  */
 381
 382 #ifdef CONFIG_TSEC_ENET
 383 #define CONFIG_MII_DEFAULT_TSEC         3
 384 #define CONFIG_TSEC1                    1
 385 #define CONFIG_TSEC1_NAME               "eTSEC1"
 386 #define CONFIG_TSEC2                    1
 387 #define CONFIG_TSEC2_NAME               "eTSEC2"
 388 #define CONFIG_TSEC3                    1
 389 #define CONFIG_TSEC3_NAME               "eTSEC3"
 390
 391 #define TSEC1_PHY_ADDR                  1
 392 #define TSEC2_PHY_ADDR                  2
 393 #define TSEC3_PHY_ADDR                  3
 394
 395 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 396 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 397 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 398
 399 #define TSEC1_PHYIDX                    0
 400 #define TSEC2_PHYIDX                    0
 401 #define TSEC3_PHYIDX                    0
 402
 403 #define CONFIG_ETHPRIME                 "eTSEC1"
 404
 405 #define CONFIG_HAS_ETH0
 406 #define CONFIG_HAS_ETH1
 407 #define CONFIG_HAS_ETH2
 408
 409 #define CONFIG_FSL_SGMII_RISER          1
 410 #define SGMII_RISER_PHY_OFFSET          0x1b
 411
 412 #ifdef CONFIG_FSL_SGMII_RISER
 413 #define CONFIG_SYS_TBIPA_VALUE          8
 414 #endif
 415
 416 #endif
 417
 418 /* PCIe */
 419 #define CONFIG_PCIE1            /* PCIE controller 1 */
 420 #define CONFIG_PCIE2            /* PCIE controller 2 */
 421
 422 #ifdef CONFIG_PCI
 423 #define CONFIG_PCI_SCAN_SHOW
 424 #endif
 425
 426 #define CONFIG_CMDLINE_TAG
 427
 428 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 429 #define CONFIG_LAYERSCAPE_NS_ACCESS
 430 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 431 #define COUNTER_FREQUENCY               12500000
 432
 433 #define CONFIG_HWCONFIG
 434 #define HWCONFIG_BUFFER_SIZE            256
 435
 436 #define CONFIG_FSL_DEVICE_DISABLE
 437
 438
 439 #define CONFIG_SYS_QE_FW_ADDR     0x60940000
 440
 441 #ifdef CONFIG_LPUART
 442 #define CONFIG_EXTRA_ENV_SETTINGS       \
 443         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 444         "initrd_high=0xffffffff\0"      \
 445         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 446 #else
 447 #define CONFIG_EXTRA_ENV_SETTINGS       \
 448         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 449         "initrd_high=0xffffffff\0"      \
 450         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 451 #endif
 452
 453 /*
 454  * Miscellaneous configurable options
 455  */
 456 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 457
 458 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 459
 460 #define CONFIG_LS102XA_STREAM_ID
 461
 462 #define CONFIG_SYS_INIT_SP_OFFSET \
 463         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 464 #define CONFIG_SYS_INIT_SP_ADDR \
 465         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 466
 467 #ifdef CONFIG_SPL_BUILD
 468 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 469 #else
 470 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 471 #endif
 472
 473 /*
 474  * Environment
 475  */
 476
 477 #include <asm/fsl_secure_boot.h>
 478 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 479
 480 #endif