include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  12
  13 #ifdef CONFIG_SD_BOOT
  14 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  15 #endif
  16
  17 #ifdef CONFIG_NAND_BOOT
  18 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  19 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  20 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  21
  22 #define CONFIG_SYS_MONITOR_LEN          0x80000
  23 #endif
  24
  25 #define SPD_EEPROM_ADDRESS              0x51
  26
  27 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  28 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  29
  30 #ifdef CONFIG_DDR_ECC
  31 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  32 #endif
  33
  34 /*
  35  * IFC Definitions
  36  */
  37 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  38 #define CONFIG_SYS_FLASH_BASE           0x60000000
  39 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  40
  41 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  42 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  43                                 CSPR_PORT_SIZE_16 | \
  44                                 CSPR_MSEL_NOR | \
  45                                 CSPR_V)
  46 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  47 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  48                                 + 0x8000000) | \
  49                                 CSPR_PORT_SIZE_16 | \
  50                                 CSPR_MSEL_NOR | \
  51                                 CSPR_V)
  52 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  53
  54 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  55                                         CSOR_NOR_TRHZ_80)
  56 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  57                                         FTIM0_NOR_TEADC(0x5) | \
  58                                         FTIM0_NOR_TEAHC(0x5))
  59 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  60                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  61                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  62 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  63                                         FTIM2_NOR_TCH(0x4) | \
  64                                         FTIM2_NOR_TWPH(0xe) | \
  65                                         FTIM2_NOR_TWP(0x1c))
  66 #define CONFIG_SYS_NOR_FTIM3            0
  67
  68 #define CONFIG_SYS_FLASH_QUIET_TEST
  69 #define CONFIG_FLASH_SHOW_PROGRESS      45
  70 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  71
  72 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  73
  74 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
  75                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  76
  77 /*
  78  * NAND Flash Definitions
  79  */
  80
  81 #define CONFIG_SYS_NAND_BASE            0x7e800000
  82 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  83
  84 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  85
  86 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  87                                 | CSPR_PORT_SIZE_8      \
  88                                 | CSPR_MSEL_NAND        \
  89                                 | CSPR_V)
  90 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
  91 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  92                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  93                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  94                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  95                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  96                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
  97                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  98
  99 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 100                                         FTIM0_NAND_TWP(0x18)   | \
 101                                         FTIM0_NAND_TWCHT(0x7) | \
 102                                         FTIM0_NAND_TWH(0xa))
 103 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 104                                         FTIM1_NAND_TWBE(0x39)  | \
 105                                         FTIM1_NAND_TRR(0xe)   | \
 106                                         FTIM1_NAND_TRP(0x18))
 107 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 108                                         FTIM2_NAND_TREH(0xa) | \
 109                                         FTIM2_NAND_TWHRE(0x1e))
 110 #define CONFIG_SYS_NAND_FTIM3           0x0
 111
 112 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 113 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 114 #endif
 115
 116 /*
 117  * QIXIS Definitions
 118  */
 119
 120 #ifdef CONFIG_FSL_QIXIS
 121 #define QIXIS_BASE                      0x7fb00000
 122 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 123 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 124 #define QIXIS_LBMAP_SWITCH              6
 125 #define QIXIS_LBMAP_MASK                0x0f
 126 #define QIXIS_LBMAP_SHIFT               0
 127 #define QIXIS_LBMAP_DFLTBANK            0x00
 128 #define QIXIS_LBMAP_ALTBANK             0x04
 129 #define QIXIS_PWR_CTL                   0x21
 130 #define QIXIS_PWR_CTL_POWEROFF          0x80
 131 #define QIXIS_RST_CTL_RESET             0x44
 132 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 133 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 134 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 135 #define QIXIS_CTL_SYS                   0x5
 136 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 137 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 138 #define QIXIS_RST_FORCE_3               0x45
 139 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 140 #define QIXIS_PWR_CTL2                  0x21
 141 #define QIXIS_PWR_CTL2_PCTL             0x2
 142
 143 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 144 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 145                                         CSPR_PORT_SIZE_8 | \
 146                                         CSPR_MSEL_GPCM | \
 147                                         CSPR_V)
 148 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 149 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 150                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 151                                         CSOR_NOR_TRHZ_80)
 152
 153 /*
 154  * QIXIS Timing parameters for IFC GPCM
 155  */
 156 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 157                                         FTIM0_GPCM_TEADC(0xe) | \
 158                                         FTIM0_GPCM_TEAHC(0xe))
 159 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 160                                         FTIM1_GPCM_TRAD(0x1f))
 161 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 162                                         FTIM2_GPCM_TCH(0xe) | \
 163                                         FTIM2_GPCM_TWP(0xf0))
 164 #define CONFIG_SYS_FPGA_FTIM3           0x0
 165 #endif
 166
 167 #if defined(CONFIG_NAND_BOOT)
 168 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 169 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 170 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 171 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 172 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 173 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 174 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 175 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 176 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 177 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 178 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 179 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 180 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 181 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 182 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 183 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 184 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 185 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 186 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 187 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 188 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 189 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 190 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 191 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 192 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 193 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 194 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 195 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 196 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 197 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 198 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 199 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 200 #else
 201 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 202 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 203 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 204 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 205 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 206 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 207 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 208 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 209 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 210 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 211 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 212 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 213 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 214 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 215 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 216 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 217 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 218 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 219 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 220 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 221 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 222 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 223 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 224 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 225 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 226 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 227 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 228 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 229 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 230 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 231 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 232 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 233 #endif
 234
 235 /*
 236  * Serial Port
 237  */
 238 #ifndef CONFIG_LPUART
 239 #define CONFIG_SYS_NS16550_SERIAL
 240 #ifndef CONFIG_DM_SERIAL
 241 #define CONFIG_SYS_NS16550_REG_SIZE     1
 242 #endif
 243 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 244 #endif
 245
 246 /*
 247  * I2C
 248  */
 249
 250 /* GPIO */
 251
 252 /* EEPROM */
 253 #define CONFIG_SYS_I2C_EEPROM_NXID
 254 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 255
 256 /*
 257  * I2C bus multiplexer
 258  */
 259 #define I2C_MUX_PCA_ADDR_PRI            0x77
 260 #define I2C_MUX_CH_DEFAULT              0x8
 261 #define I2C_MUX_CH_CH7301               0xC
 262
 263 /*
 264  * MMC
 265  */
 266
 267 /*
 268  * eTSEC
 269  */
 270
 271 #ifdef CONFIG_TSEC_ENET
 272 #define CONFIG_MII_DEFAULT_TSEC         3
 273 #define CONFIG_TSEC1                    1
 274 #define CONFIG_TSEC1_NAME               "eTSEC1"
 275 #define CONFIG_TSEC2                    1
 276 #define CONFIG_TSEC2_NAME               "eTSEC2"
 277 #define CONFIG_TSEC3                    1
 278 #define CONFIG_TSEC3_NAME               "eTSEC3"
 279
 280 #define TSEC1_PHY_ADDR                  1
 281 #define TSEC2_PHY_ADDR                  2
 282 #define TSEC3_PHY_ADDR                  3
 283
 284 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 285 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 286 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 287
 288 #define TSEC1_PHYIDX                    0
 289 #define TSEC2_PHYIDX                    0
 290 #define TSEC3_PHYIDX                    0
 291
 292 #define CONFIG_FSL_SGMII_RISER          1
 293 #define SGMII_RISER_PHY_OFFSET          0x1b
 294
 295 #ifdef CONFIG_FSL_SGMII_RISER
 296 #define CONFIG_SYS_TBIPA_VALUE          8
 297 #endif
 298
 299 #endif
 300
 301 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 302 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 303
 304 #define CONFIG_HWCONFIG
 305 #define HWCONFIG_BUFFER_SIZE            256
 306
 307 #define CONFIG_FSL_DEVICE_DISABLE
 308
 309 #ifdef CONFIG_LPUART
 310 #define CONFIG_EXTRA_ENV_SETTINGS       \
 311         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 312         "initrd_high=0xffffffff\0"      \
 313         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 314 #else
 315 #define CONFIG_EXTRA_ENV_SETTINGS       \
 316         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 317         "initrd_high=0xffffffff\0"      \
 318         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 319 #endif
 320
 321 /*
 322  * Miscellaneous configurable options
 323  */
 324 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 325
 326 #define CONFIG_LS102XA_STREAM_ID
 327
 328 /*
 329  * Environment
 330  */
 331
 332 #include <asm/fsl_secure_boot.h>
 333
 334 #endif