1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2014 Freescale Semiconductor, Inc.
10 #define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
11 #define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
13 #ifdef CONFIG_NAND_BOOT
14 #define CFG_SYS_NAND_U_BOOT_SIZE (400 << 10)
15 #define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
16 #define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
20 #define SPD_EEPROM_ADDRESS 0x51
22 #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
23 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
26 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
32 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
33 #define CFG_SYS_FLASH_BASE 0x60000000
34 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
36 #define CFG_SYS_NOR0_CSPR_EXT (0x0)
37 #define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
41 #define CFG_SYS_NOR1_CSPR_EXT (0x0)
42 #define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
47 #define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
49 #define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
51 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
52 FTIM0_NOR_TEADC(0x5) | \
54 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
55 FTIM1_NOR_TRAD_NOR(0x1a) | \
56 FTIM1_NOR_TSEQRAD_NOR(0x13))
57 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
58 FTIM2_NOR_TCH(0x4) | \
59 FTIM2_NOR_TWPH(0xe) | \
61 #define CFG_SYS_NOR_FTIM3 0
63 #define CFG_SYS_WRITE_SWAPPED_DATA
65 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \
66 CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
69 * NAND Flash Definitions
72 #define CFG_SYS_NAND_BASE 0x7e800000
73 #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
75 #define CFG_SYS_NAND_CSPR_EXT (0x0)
77 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
81 #define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
82 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
83 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
84 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
85 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
86 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
87 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
88 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
90 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
91 FTIM0_NAND_TWP(0x18) | \
92 FTIM0_NAND_TWCHT(0x7) | \
94 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
95 FTIM1_NAND_TWBE(0x39) | \
96 FTIM1_NAND_TRR(0xe) | \
98 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
99 FTIM2_NAND_TREH(0xa) | \
100 FTIM2_NAND_TWHRE(0x1e))
101 #define CFG_SYS_NAND_FTIM3 0x0
103 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
110 #ifdef CONFIG_FSL_QIXIS
111 #define QIXIS_BASE 0x7fb00000
112 #define QIXIS_BASE_PHYS QIXIS_BASE
113 #define CFG_SYS_I2C_FPGA_ADDR 0x66
114 #define QIXIS_LBMAP_SWITCH 6
115 #define QIXIS_LBMAP_MASK 0x0f
116 #define QIXIS_LBMAP_SHIFT 0
117 #define QIXIS_LBMAP_DFLTBANK 0x00
118 #define QIXIS_LBMAP_ALTBANK 0x04
119 #define QIXIS_PWR_CTL 0x21
120 #define QIXIS_PWR_CTL_POWEROFF 0x80
121 #define QIXIS_RST_CTL_RESET 0x44
122 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
123 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
124 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
125 #define QIXIS_CTL_SYS 0x5
126 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
127 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
128 #define QIXIS_RST_FORCE_3 0x45
129 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
130 #define QIXIS_PWR_CTL2 0x21
131 #define QIXIS_PWR_CTL2_PCTL 0x2
133 #define CFG_SYS_FPGA_CSPR_EXT (0x0)
134 #define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
138 #define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
139 #define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
140 CSOR_NOR_NOR_MODE_AVD_NOR | \
144 * QIXIS Timing parameters for IFC GPCM
146 #define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
147 FTIM0_GPCM_TEADC(0xe) | \
148 FTIM0_GPCM_TEAHC(0xe))
149 #define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
150 FTIM1_GPCM_TRAD(0x1f))
151 #define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
152 FTIM2_GPCM_TCH(0xe) | \
153 FTIM2_GPCM_TWP(0xf0))
154 #define CFG_SYS_FPGA_FTIM3 0x0
157 #if defined(CONFIG_NAND_BOOT)
158 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
159 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
160 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
161 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
162 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
163 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
164 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
165 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
166 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
167 #define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
168 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
169 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
170 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
171 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
172 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
173 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
174 #define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
175 #define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
176 #define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
177 #define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
178 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
179 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
180 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
181 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
182 #define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
183 #define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
184 #define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
185 #define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
186 #define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
187 #define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
188 #define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
189 #define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
191 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
192 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
193 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
194 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
195 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
196 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
197 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
198 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
199 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
200 #define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
201 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
202 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
203 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
204 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
205 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
206 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
207 #define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
208 #define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
209 #define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
210 #define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
211 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
212 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
213 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
214 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
215 #define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
216 #define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
217 #define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK
218 #define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
219 #define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0
220 #define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1
221 #define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2
222 #define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3
228 #ifndef CONFIG_LPUART
229 #define CFG_SYS_NS16550_CLK get_serial_clock()
239 * I2C bus multiplexer
241 #define I2C_MUX_PCA_ADDR_PRI 0x77
242 #define I2C_MUX_CH_DEFAULT 0x8
243 #define I2C_MUX_CH_CH7301 0xC
249 #define CONFIG_PEN_ADDR_BIG_ENDIAN
250 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
252 #define HWCONFIG_BUFFER_SIZE 256
255 #define CONFIG_EXTRA_ENV_SETTINGS \
256 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
257 "initrd_high=0xffffffff\0" \
258 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
260 #define CONFIG_EXTRA_ENV_SETTINGS \
261 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
262 "initrd_high=0xffffffff\0" \
263 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
267 * Miscellaneous configurable options
269 #define CFG_SYS_BOOTMAPSZ (256 << 20)
275 #include <asm/fsl_secure_boot.h>