include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  11 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  12
  13 #ifdef CONFIG_SD_BOOT
  14 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  15 #endif
  16
  17 #ifdef CONFIG_NAND_BOOT
  18 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
  19 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
  20 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
  21
  22 #define CONFIG_SYS_MONITOR_LEN          0x80000
  23 #endif
  24
  25 #define SPD_EEPROM_ADDRESS              0x51
  26 #define CONFIG_SYS_SPD_BUS_NUM          0
  27
  28 #ifndef CONFIG_SYS_FSL_DDR4
  29 #define CONFIG_SYS_DDR_RAW_TIMING
  30 #endif
  31
  32 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  33 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  34
  35 #ifdef CONFIG_DDR_ECC
  36 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  37 #endif
  38
  39 /*
  40  * IFC Definitions
  41  */
  42 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  43 #define CONFIG_SYS_FLASH_BASE           0x60000000
  44 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  45
  46 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  47 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  48                                 CSPR_PORT_SIZE_16 | \
  49                                 CSPR_MSEL_NOR | \
  50                                 CSPR_V)
  51 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
  52 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  53                                 + 0x8000000) | \
  54                                 CSPR_PORT_SIZE_16 | \
  55                                 CSPR_MSEL_NOR | \
  56                                 CSPR_V)
  57 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  58
  59 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  60                                         CSOR_NOR_TRHZ_80)
  61 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  62                                         FTIM0_NOR_TEADC(0x5) | \
  63                                         FTIM0_NOR_TEAHC(0x5))
  64 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  65                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  66                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  67 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  68                                         FTIM2_NOR_TCH(0x4) | \
  69                                         FTIM2_NOR_TWPH(0xe) | \
  70                                         FTIM2_NOR_TWP(0x1c))
  71 #define CONFIG_SYS_NOR_FTIM3            0
  72
  73 #define CONFIG_SYS_FLASH_QUIET_TEST
  74 #define CONFIG_FLASH_SHOW_PROGRESS      45
  75 #define CONFIG_SYS_WRITE_SWAPPED_DATA
  76
  77 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  78 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  79 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  80
  81 #define CONFIG_SYS_FLASH_EMPTY_INFO
  82 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
  83                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  84
  85 /*
  86  * NAND Flash Definitions
  87  */
  88
  89 #define CONFIG_SYS_NAND_BASE            0x7e800000
  90 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  91
  92 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  93
  94 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  95                                 | CSPR_PORT_SIZE_8      \
  96                                 | CSPR_MSEL_NAND        \
  97                                 | CSPR_V)
  98 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
  99 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 100                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 101                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 102                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 103                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 104                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 105                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 106
 107 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 108                                         FTIM0_NAND_TWP(0x18)   | \
 109                                         FTIM0_NAND_TWCHT(0x7) | \
 110                                         FTIM0_NAND_TWH(0xa))
 111 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 112                                         FTIM1_NAND_TWBE(0x39)  | \
 113                                         FTIM1_NAND_TRR(0xe)   | \
 114                                         FTIM1_NAND_TRP(0x18))
 115 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 116                                         FTIM2_NAND_TREH(0xa) | \
 117                                         FTIM2_NAND_TWHRE(0x1e))
 118 #define CONFIG_SYS_NAND_FTIM3           0x0
 119
 120 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 121 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 122 #endif
 123
 124 /*
 125  * QIXIS Definitions
 126  */
 127
 128 #ifdef CONFIG_FSL_QIXIS
 129 #define QIXIS_BASE                      0x7fb00000
 130 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 131 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 132 #define QIXIS_LBMAP_SWITCH              6
 133 #define QIXIS_LBMAP_MASK                0x0f
 134 #define QIXIS_LBMAP_SHIFT               0
 135 #define QIXIS_LBMAP_DFLTBANK            0x00
 136 #define QIXIS_LBMAP_ALTBANK             0x04
 137 #define QIXIS_PWR_CTL                   0x21
 138 #define QIXIS_PWR_CTL_POWEROFF          0x80
 139 #define QIXIS_RST_CTL_RESET             0x44
 140 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 141 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 142 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 143 #define QIXIS_CTL_SYS                   0x5
 144 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 145 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 146 #define QIXIS_RST_FORCE_3               0x45
 147 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 148 #define QIXIS_PWR_CTL2                  0x21
 149 #define QIXIS_PWR_CTL2_PCTL             0x2
 150
 151 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 152 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 153                                         CSPR_PORT_SIZE_8 | \
 154                                         CSPR_MSEL_GPCM | \
 155                                         CSPR_V)
 156 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 157 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 158                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 159                                         CSOR_NOR_TRHZ_80)
 160
 161 /*
 162  * QIXIS Timing parameters for IFC GPCM
 163  */
 164 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 165                                         FTIM0_GPCM_TEADC(0xe) | \
 166                                         FTIM0_GPCM_TEAHC(0xe))
 167 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 168                                         FTIM1_GPCM_TRAD(0x1f))
 169 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 170                                         FTIM2_GPCM_TCH(0xe) | \
 171                                         FTIM2_GPCM_TWP(0xf0))
 172 #define CONFIG_SYS_FPGA_FTIM3           0x0
 173 #endif
 174
 175 #if defined(CONFIG_NAND_BOOT)
 176 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 177 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 178 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 179 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 180 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 181 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 182 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 183 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 184 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 185 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 186 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 187 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 188 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 189 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 190 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 191 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 192 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 193 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 194 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 195 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 196 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 197 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 198 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 199 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 200 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 201 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 202 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 203 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 204 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 205 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 206 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 207 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 208 #else
 209 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 210 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 211 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 212 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 213 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 214 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 215 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 216 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 217 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 218 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 219 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 220 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 221 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 222 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 223 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 224 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 225 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 226 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 227 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 228 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 229 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 230 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 231 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 232 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 233 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 234 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 235 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 236 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 237 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 238 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 239 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 240 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 241 #endif
 242
 243 /*
 244  * Serial Port
 245  */
 246 #ifndef CONFIG_LPUART
 247 #define CONFIG_SYS_NS16550_SERIAL
 248 #ifndef CONFIG_DM_SERIAL
 249 #define CONFIG_SYS_NS16550_REG_SIZE     1
 250 #endif
 251 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 252 #endif
 253
 254 /*
 255  * I2C
 256  */
 257
 258 /* GPIO */
 259
 260 /* EEPROM */
 261 #define CONFIG_SYS_I2C_EEPROM_NXID
 262 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 263
 264 /*
 265  * I2C bus multiplexer
 266  */
 267 #define I2C_MUX_PCA_ADDR_PRI            0x77
 268 #define I2C_MUX_CH_DEFAULT              0x8
 269 #define I2C_MUX_CH_CH7301               0xC
 270
 271 /*
 272  * MMC
 273  */
 274
 275 /*
 276  * eTSEC
 277  */
 278
 279 #ifdef CONFIG_TSEC_ENET
 280 #define CONFIG_MII_DEFAULT_TSEC         3
 281 #define CONFIG_TSEC1                    1
 282 #define CONFIG_TSEC1_NAME               "eTSEC1"
 283 #define CONFIG_TSEC2                    1
 284 #define CONFIG_TSEC2_NAME               "eTSEC2"
 285 #define CONFIG_TSEC3                    1
 286 #define CONFIG_TSEC3_NAME               "eTSEC3"
 287
 288 #define TSEC1_PHY_ADDR                  1
 289 #define TSEC2_PHY_ADDR                  2
 290 #define TSEC3_PHY_ADDR                  3
 291
 292 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 293 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 294 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 295
 296 #define TSEC1_PHYIDX                    0
 297 #define TSEC2_PHYIDX                    0
 298 #define TSEC3_PHYIDX                    0
 299
 300 #define CONFIG_FSL_SGMII_RISER          1
 301 #define SGMII_RISER_PHY_OFFSET          0x1b
 302
 303 #ifdef CONFIG_FSL_SGMII_RISER
 304 #define CONFIG_SYS_TBIPA_VALUE          8
 305 #endif
 306
 307 #endif
 308
 309 /* PCIe */
 310 #define CONFIG_PCIE1            /* PCIE controller 1 */
 311 #define CONFIG_PCIE2            /* PCIE controller 2 */
 312
 313 #ifdef CONFIG_PCI
 314 #define CONFIG_PCI_SCAN_SHOW
 315 #endif
 316
 317 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 318 #define CONFIG_LAYERSCAPE_NS_ACCESS
 319 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 320
 321 #define CONFIG_HWCONFIG
 322 #define HWCONFIG_BUFFER_SIZE            256
 323
 324 #define CONFIG_FSL_DEVICE_DISABLE
 325
 326 #ifdef CONFIG_LPUART
 327 #define CONFIG_EXTRA_ENV_SETTINGS       \
 328         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 329         "initrd_high=0xffffffff\0"      \
 330         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 331 #else
 332 #define CONFIG_EXTRA_ENV_SETTINGS       \
 333         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 334         "initrd_high=0xffffffff\0"      \
 335         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 336 #endif
 337
 338 /*
 339  * Miscellaneous configurable options
 340  */
 341 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 342
 343 #define CONFIG_LS102XA_STREAM_ID
 344
 345 /*
 346  * Environment
 347  */
 348
 349 #include <asm/fsl_secure_boot.h>
 350 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 351
 352 #endif