include/configs/ls1021aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CFG_SYS_INIT_RAM_ADDR   OCRAM_BASE_ADDR
  11 #define CFG_SYS_INIT_RAM_SIZE   OCRAM_SIZE
  12
  13 #ifdef CONFIG_NAND_BOOT
  14 #define CFG_SYS_NAND_U_BOOT_SIZE        (400 << 10)
  15 #define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
  16 #define CFG_SYS_NAND_U_BOOT_START       CONFIG_TEXT_BASE
  17
  18 #endif
  19
  20 #define SPD_EEPROM_ADDRESS              0x51
  21
  22 #define CFG_SYS_DDR_SDRAM_BASE  0x80000000UL
  23 #define CFG_SYS_SDRAM_BASE              CFG_SYS_DDR_SDRAM_BASE
  24
  25 #ifdef CONFIG_DDR_ECC
  26 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  27 #endif
  28
  29 /*
  30  * IFC Definitions
  31  */
  32 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  33 #define CFG_SYS_FLASH_BASE              0x60000000
  34 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
  35
  36 #define CFG_SYS_NOR0_CSPR_EXT   (0x0)
  37 #define CFG_SYS_NOR0_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
  38                                 CSPR_PORT_SIZE_16 | \
  39                                 CSPR_MSEL_NOR | \
  40                                 CSPR_V)
  41 #define CFG_SYS_NOR1_CSPR_EXT   (0x0)
  42 #define CFG_SYS_NOR1_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
  43                                 + 0x8000000) | \
  44                                 CSPR_PORT_SIZE_16 | \
  45                                 CSPR_MSEL_NOR | \
  46                                 CSPR_V)
  47 #define CFG_SYS_NOR_AMASK               IFC_AMASK(128 * 1024 * 1024)
  48
  49 #define CFG_SYS_NOR_CSOR                (CSOR_NOR_ADM_SHIFT(4) | \
  50                                         CSOR_NOR_TRHZ_80)
  51 #define CFG_SYS_NOR_FTIM0               (FTIM0_NOR_TACSE(0x4) | \
  52                                         FTIM0_NOR_TEADC(0x5) | \
  53                                         FTIM0_NOR_TEAHC(0x5))
  54 #define CFG_SYS_NOR_FTIM1               (FTIM1_NOR_TACO(0x35) | \
  55                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
  56                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  57 #define CFG_SYS_NOR_FTIM2               (FTIM2_NOR_TCS(0x4) | \
  58                                         FTIM2_NOR_TCH(0x4) | \
  59                                         FTIM2_NOR_TWPH(0xe) | \
  60                                         FTIM2_NOR_TWP(0x1c))
  61 #define CFG_SYS_NOR_FTIM3               0
  62
  63 #define CONFIG_FLASH_SHOW_PROGRESS      45
  64 #define CFG_SYS_WRITE_SWAPPED_DATA
  65
  66 #define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS, \
  67                                         CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
  68
  69 /*
  70  * NAND Flash Definitions
  71  */
  72
  73 #define CFG_SYS_NAND_BASE               0x7e800000
  74 #define CFG_SYS_NAND_BASE_PHYS  CFG_SYS_NAND_BASE
  75
  76 #define CFG_SYS_NAND_CSPR_EXT   (0x0)
  77
  78 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
  79                                 | CSPR_PORT_SIZE_8      \
  80                                 | CSPR_MSEL_NAND        \
  81                                 | CSPR_V)
  82 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
  83 #define CFG_SYS_NAND_CSOR       (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  84                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  85                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  86                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  87                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  88                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
  89                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  90
  91 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x7) | \
  92                                         FTIM0_NAND_TWP(0x18)   | \
  93                                         FTIM0_NAND_TWCHT(0x7) | \
  94                                         FTIM0_NAND_TWH(0xa))
  95 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
  96                                         FTIM1_NAND_TWBE(0x39)  | \
  97                                         FTIM1_NAND_TRR(0xe)   | \
  98                                         FTIM1_NAND_TRP(0x18))
  99 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0xf) | \
 100                                         FTIM2_NAND_TREH(0xa) | \
 101                                         FTIM2_NAND_TWHRE(0x1e))
 102 #define CFG_SYS_NAND_FTIM3           0x0
 103
 104 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 105 #endif
 106
 107 /*
 108  * QIXIS Definitions
 109  */
 110
 111 #ifdef CONFIG_FSL_QIXIS
 112 #define QIXIS_BASE                      0x7fb00000
 113 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 114 #define CFG_SYS_I2C_FPGA_ADDR   0x66
 115 #define QIXIS_LBMAP_SWITCH              6
 116 #define QIXIS_LBMAP_MASK                0x0f
 117 #define QIXIS_LBMAP_SHIFT               0
 118 #define QIXIS_LBMAP_DFLTBANK            0x00
 119 #define QIXIS_LBMAP_ALTBANK             0x04
 120 #define QIXIS_PWR_CTL                   0x21
 121 #define QIXIS_PWR_CTL_POWEROFF          0x80
 122 #define QIXIS_RST_CTL_RESET             0x44
 123 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 124 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 125 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 126 #define QIXIS_CTL_SYS                   0x5
 127 #define QIXIS_CTL_SYS_EVTSW_MASK        0x0c
 128 #define QIXIS_CTL_SYS_EVTSW_IRQ         0x04
 129 #define QIXIS_RST_FORCE_3               0x45
 130 #define QIXIS_RST_FORCE_3_PCIESLOT1     0x80
 131 #define QIXIS_PWR_CTL2                  0x21
 132 #define QIXIS_PWR_CTL2_PCTL             0x2
 133
 134 #define CFG_SYS_FPGA_CSPR_EXT   (0x0)
 135 #define CFG_SYS_FPGA_CSPR               (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 136                                         CSPR_PORT_SIZE_8 | \
 137                                         CSPR_MSEL_GPCM | \
 138                                         CSPR_V)
 139 #define CFG_SYS_FPGA_AMASK              IFC_AMASK(64 * 1024)
 140 #define CFG_SYS_FPGA_CSOR               (CSOR_NOR_ADM_SHIFT(4) | \
 141                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 142                                         CSOR_NOR_TRHZ_80)
 143
 144 /*
 145  * QIXIS Timing parameters for IFC GPCM
 146  */
 147 #define CFG_SYS_FPGA_FTIM0              (FTIM0_GPCM_TACSE(0xe) | \
 148                                         FTIM0_GPCM_TEADC(0xe) | \
 149                                         FTIM0_GPCM_TEAHC(0xe))
 150 #define CFG_SYS_FPGA_FTIM1              (FTIM1_GPCM_TACO(0xe) | \
 151                                         FTIM1_GPCM_TRAD(0x1f))
 152 #define CFG_SYS_FPGA_FTIM2              (FTIM2_GPCM_TCS(0xe) | \
 153                                         FTIM2_GPCM_TCH(0xe) | \
 154                                         FTIM2_GPCM_TWP(0xf0))
 155 #define CFG_SYS_FPGA_FTIM3              0x0
 156 #endif
 157
 158 #if defined(CONFIG_NAND_BOOT)
 159 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 160 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 161 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 162 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 163 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 164 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 165 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 166 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 167 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR0_CSPR_EXT
 168 #define CFG_SYS_CSPR1           CFG_SYS_NOR0_CSPR
 169 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 170 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 171 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 172 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 173 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 174 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 175 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NOR1_CSPR_EXT
 176 #define CFG_SYS_CSPR2           CFG_SYS_NOR1_CSPR
 177 #define CFG_SYS_AMASK2          CFG_SYS_NOR_AMASK
 178 #define CFG_SYS_CSOR2           CFG_SYS_NOR_CSOR
 179 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NOR_FTIM0
 180 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NOR_FTIM1
 181 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NOR_FTIM2
 182 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NOR_FTIM3
 183 #define CFG_SYS_CSPR3_EXT               CFG_SYS_FPGA_CSPR_EXT
 184 #define CFG_SYS_CSPR3           CFG_SYS_FPGA_CSPR
 185 #define CFG_SYS_AMASK3          CFG_SYS_FPGA_AMASK
 186 #define CFG_SYS_CSOR3           CFG_SYS_FPGA_CSOR
 187 #define CFG_SYS_CS3_FTIM0               CFG_SYS_FPGA_FTIM0
 188 #define CFG_SYS_CS3_FTIM1               CFG_SYS_FPGA_FTIM1
 189 #define CFG_SYS_CS3_FTIM2               CFG_SYS_FPGA_FTIM2
 190 #define CFG_SYS_CS3_FTIM3               CFG_SYS_FPGA_FTIM3
 191 #else
 192 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 193 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR
 194 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 195 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 196 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 197 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 198 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 199 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 200 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR1_CSPR_EXT
 201 #define CFG_SYS_CSPR1           CFG_SYS_NOR1_CSPR
 202 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 203 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 204 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 205 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 206 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 207 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 208 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NAND_CSPR_EXT
 209 #define CFG_SYS_CSPR2           CFG_SYS_NAND_CSPR
 210 #define CFG_SYS_AMASK2          CFG_SYS_NAND_AMASK
 211 #define CFG_SYS_CSOR2           CFG_SYS_NAND_CSOR
 212 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NAND_FTIM0
 213 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NAND_FTIM1
 214 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NAND_FTIM2
 215 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NAND_FTIM3
 216 #define CFG_SYS_CSPR3_EXT               CFG_SYS_FPGA_CSPR_EXT
 217 #define CFG_SYS_CSPR3           CFG_SYS_FPGA_CSPR
 218 #define CFG_SYS_AMASK3          CFG_SYS_FPGA_AMASK
 219 #define CFG_SYS_CSOR3           CFG_SYS_FPGA_CSOR
 220 #define CFG_SYS_CS3_FTIM0               CFG_SYS_FPGA_FTIM0
 221 #define CFG_SYS_CS3_FTIM1               CFG_SYS_FPGA_FTIM1
 222 #define CFG_SYS_CS3_FTIM2               CFG_SYS_FPGA_FTIM2
 223 #define CFG_SYS_CS3_FTIM3               CFG_SYS_FPGA_FTIM3
 224 #endif
 225
 226 /*
 227  * Serial Port
 228  */
 229 #ifndef CONFIG_LPUART
 230 #define CFG_SYS_NS16550_CLK             get_serial_clock()
 231 #endif
 232
 233 /*
 234  * I2C
 235  */
 236
 237 /* GPIO */
 238
 239 /*
 240  * I2C bus multiplexer
 241  */
 242 #define I2C_MUX_PCA_ADDR_PRI            0x77
 243 #define I2C_MUX_CH_DEFAULT              0x8
 244 #define I2C_MUX_CH_CH7301               0xC
 245
 246 /*
 247  * MMC
 248  */
 249
 250 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 251 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 252
 253 #define HWCONFIG_BUFFER_SIZE            256
 254
 255 #ifdef CONFIG_LPUART
 256 #define CONFIG_EXTRA_ENV_SETTINGS       \
 257         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 258         "initrd_high=0xffffffff\0"      \
 259         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 260 #else
 261 #define CONFIG_EXTRA_ENV_SETTINGS       \
 262         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 263         "initrd_high=0xffffffff\0"      \
 264         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 265 #endif
 266
 267 /*
 268  * Miscellaneous configurable options
 269  */
 270 #define CFG_SYS_BOOTMAPSZ               (256 << 20)
 271
 272 /*
 273  * Environment
 274  */
 275
 276 #include <asm/fsl_secure_boot.h>
 277
 278 #endif